k7a803601m Samsung Semiconductor, Inc., k7a803601m Datasheet - Page 5

• Manufacturer Part Number: k7a803601m
• Description: 256kx36 & 512kx18 Synchronous Sram
• Manufacturer: Samsung Semiconductor, Inc.

K7A803601M
K7A801801M
FUNCTION DESCRIPTION
The K7A803601M and K7A801801M are synchronous SRAM designed to support the burst address accessing sequence of the
Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and
duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address
register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-
ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-
ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output
pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to
control signals by disabling CS
All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx
when GW is high.
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-
ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled
Low(regaedless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte
write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa
and DQPb, WEc controls DQc
ated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is selected.
BURST SEQUENCE TABLE
BQ TABLE
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed
ASYNCHRONOUS TRUTH TABLE
LBO PIN
LBO PIN
OPERATION
Sleep Mode
Deselected
Fourth Address
Fourth Address
First Address
Read
First Address
Write
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).
HIGH
LOW
0
1
.
~ DQc
ZZ
H
L
L
L
L
7
and DQPc, and WEd control DQd
OE
X
H
X
X
L
A
A
0
0
1
1
0
0
1
1
1
1
Case 1
Case 1
Din, High-Z
I/O Status
High-Z
High-Z
High-Z
DQ
A
A
256Kx36 & 512Kx18 Synchronous SRAM
0
1
0
1
0
1
0
1
0
0
- 5 -
A
A
0
0
1
1
0
1
1
0
Notes
1. X means "Don t Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must be
4. Sleep Mode means power down state of which stand-by current does
5. Deselected means power down state of which stand-by current
1
1
Case 2
Case 2
disabled with OE, otherwise data bus contention will occur.
not depend on cycle time.
depends on cycle time.
0
~ DQd
.
A
A
1
0
1
0
1
0
1
0
0
0
7
0
and DQPd. Read or write cycle may also be initi-
~ DQa
A
A
1
1
0
0
7
1
1
0
0
1
1
and DQPa, WEb controls DQb
Case 3
Case 3
A
A
0
1
0
1
0
1
0
1
0
0
A
1
1
0
0
A
(Interleaved Burst)
1
0
0
1
1
1
Case 4
Case 4
(Linear Burst)
May 1999
0
Rev 3.0
~ DQb
A
A
1
0
1
0
1
0
1
0
0
0
7