k7a803601m Samsung Semiconductor, Inc., k7a803601m Datasheet - Page 15

• Manufacturer Part Number: k7a803601m
• Description: 256kx36 & 512kx18 Synchronous Sram
• Manufacturer: Samsung Semiconductor, Inc.

K7A803601M
K7A801801M
INTERLEAVE READ TIMING
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 256Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic.
Microprocessor
(ADSP CONTROLLED , ADSC=HIGH)
Clock
ADSP
ADDRESS
[0:n*]
WRITE
CS
A
ADV
OE
Data Out
(Bank 0)
Data Out
(Bank 1)
n+1*
1
Address
t
SS
Data
ADS
CLK
*Notes : n = 14 32K depth ,
A1
t
SH
t
WS
Bank 0 is selected by CS
16 128K depth ,
18 512K depth
t
A
LZOE
[0:18]
t
ADVS
t
t
WH
OE
CLK
Q1-1
(Refer to non-interleave write timing for interleave write timing)
Cache
Controller
Address
t
ADVH
15 64K depth
17 256K depth
Q1-2
2
, and Bank 1 deselected by CS
256Kx36 & 512Kx18 Synchronous SRAM
t
CSS
t
AS
Q1-3
A
A2
- 15 -
[18]
t
t
CSH
AH
t
HZC
t
LZC
t
A
Q1-4
CD
CS
CS
CLK
ADSC
WEx
OE
CS
[0:17]
Bank 0 is deselected by CS
Address Data
ADV
2
2
1
2
Q2-1
256Kx36
SPB
SRAM
(Bank 0)
ADSP
Q2-2
I/O
A
[0:71]
2
, and Bank 1 selected by CS
[18]
Q2-3
Don t Care
A
[0:17]
CS
CS
CLK
ADSC
WEx
OE
CS
Address Data
ADV
2
2
1
Q2-4
256Kx36
SPB
SRAM
(Bank 1)
ADSP
May 1999
Undefined
2
Rev 3.0