lc89052t Sanyo Semiconductor Corporation, lc89052t Datasheet - Page 11

• Manufacturer Part Number: lc89052t
• Description: Digital Audio Interface Receiver
• Manufacturer: Sanyo Semiconductor Corporation

8.3 Clocks
8.3.1 PLL (LPF)
The LC89052T incorporates a VCO (Voltage Controlled Oscillator) that can synchronize with sampling frequencies
The locking frequency is selected with PLLCK[1:0]. The VCO circuit can be stopped with PLLOPR.
The range of input data that can be received differs depending on the settings of PLLCK[1:0].
The (512/2)fs for the PLLCK[1:0] = "11" in the table below is the state where the PLL itself is synchronized with the
We recommend the 256fs setting with PLLCK[1:0] = "00" for the systems such as portable equipment that need to
LPF is the PLL loop filter connection pin. Use the correct recommended resistance and capacitance as values listed in
of 30kHz to 195kHz.
512fs clock, but the clock signal output from the CKOUT pin is 1/2 of the PLL locked frequency, which is 256fs.
See the chapter on the of output clock for further information.
restrain the consumption electric power. We also recommend the 512fs setting with PLLCK[1:0] = "10" or the
(512/2)fs with PLLCK[1:0] = "11" for the systems such as AV amplifiers that require improved performance.
the table below according to the PLLCK[1:0] settings.
PLLCK1
0
0
1
1
C0
R0
LPF
Table 8.3 Input Data Reception Ranges and PLL Lock Frequency Settings
C1
PLLCK0
0
1
0
1
Figure 8.2 PLL Loop Filter Configuration
PLLCK1
0
0
1
1
PLL lock frequency
LC89052T
(512/2)fs
256fs
384fs
512fs
PLLCK0
0
1
0
1
150
150
R0
Input data reception range
0.047 F
0.068 F
30k to 195kHz
30k to 108kHz
30k to 108kHz
30k to 108kHz
C0
No.7457-11/42
0.0068 F
0.0047 F
C1