lc89052t Sanyo Semiconductor Corporation, lc89052t Datasheet - Page 31

• Manufacturer Part Number: lc89052t
• Description: Digital Audio Interface Receiver
• Manufacturer: Sanyo Semiconductor Corporation

9.6.2 Details of write data
It is possible to maintain clock continuity when switching from the 512fs setting with PLLCK[1:0] = "10" to the
For systems that must minimize power consumption such as portable equipment, we recommend the PLLCK[1:0] =
(512/2) fs setting with PLLCK[1:0] = "11", and switching vice versa without entering the PLL lock error state.
"00" (256fs) setting. For systems that require improved performance such as AV amplifiers, we recommend the
PLLCK[1:0] = "10" (512fs) or PLLCK[1:0] = "11" (512/2fs) setting.
MCKHFO
XISEL3
DI15
DI7
SYSRST:
PDOWN[1:0]:
PLLOPR:
PLLCK[1:0]:
MCKHFO:
PLLCK1
XISEL2
DI14
DI6
Table 9.5 Input Register Function Settings 1: System Settings (0xE8)
Low power mode settings (Only specific functions are enabled.)
Frequency setting of CKOUT output clock
System reset
0: No reset performed (initial value)
1: Reset all circuits other than the command registers.
00: Normal operation (initial value)
01: Only the oscillator amplifier is enabled.
10: Only the oscillator amplifier and the output clock divider are enabled.
11: Reserved
PLL (VCO) operate/stop setting
0: Operate (initial value)
1: Stop
Clock frequency setting in the PLL locked state
00: 256fs (initial value)
01: 384fs
10: 512fs
11: (512/2)fs = 256fs
0: 1/1 output (initial value)
1: 1/2 output
PLLCK0
XISEL1
DI13
DI5
PLLOPR
XISEL0
DI12
DI4
LC89052T
PDOWN1
OCKSEL
DI11
DI3
PDOWN0
AMPCNT
DI10
DI2
AMPOPR
DI1
DI9
0
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SYSRST
DI0
DI8
0