w65c22 Western Design Center, Inc., w65c22 Datasheet - Page 22

• Manufacturer Part Number: w65c22
• Description: W65c22n And W65c22s Versatile Interface Adapter Via Datasheet
• Manufacturer: Western Design Center, Inc.

2.12.2 Shift In - Counter T2 Control (001)
2.12.3 Shift In - PHI2 Clock Control (010)
In this mode, the shifting rate is controlled by the low order eight bits of counter T2. Shift pulses are
generated on the CB1 line to control shifting in external devices. The time between transitions of
the CB1 output clock is determined by the PHI2 clock period and the contents of the low order T2
latch (N). Shifting occurs by writing or reading the SR. Data is shifted into the low order bit first,
and is then shifted into the next higher order bit on the negative going edge of each clock pulse.
Input data should change before the positive going edge of the CB1 clock pulse. This data is then
shifted into the SR during the PHI2 clock cycle following the positive going edge of the CB1 clock
pulse. After eight CB1 clock pulses, IFR2 will set and IRQB will go to a Logic 0. See Figure 2-6.
In this mode, the shift rate is controlled by the PHI2 clock frequency. Shift pulses are generated on
the CB1 line to control shifting in external devices. Timer 2 operates as an independent interval
time and has no influence on the SR. Shifting occurs by reading or writing the SR. Data is shifted
into the low order bit first, and is then shifted into the next higher order bit on the trailing edge of the
PHI2 clock pulse. After eight clock pulses, IFR2 will be set, and output clock pulses on the CB1 line
will stop. See Figure 2-7.
Figure 2-6 Shift In - Counter T2 Control
Figure 2-7 Shift In - PHI2 Clock Control
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