w65c22 Western Design Center, Inc., w65c22 Datasheet - Page 35

• Manufacturer Part Number: w65c22
• Description: W65c22n And W65c22s Versatile Interface Adapter Via Datasheet
• Manufacturer: Western Design Center, Inc.

The system PHI2 Input Clock controls all data transfers between the W65C22 and the microprocessor .
Reset clears all internal registers (except T1 and T2 counters and latches, and the SR. In the RESB
condition, all pins are placed in the input state and bus holding devices maintain initial level if not driven.
The initial level can be Logic 1 or Logic 0 and are not initialized by on chip circuitry. Also, T1 and T2, SR
and the interrupt logic are disabled from operation. All inputs have NOR gates with reset overriding the
input pin value. Schmitt trigger NOR gates are on CA1, CA2, DB1, CB2, and PH2. Reset has a Schmitt
trigger inverter input. The W65C22S RESB input has a bus holding device.
The RS0-RS3 inputs allow the microprocessor to select one of 16 internal registers within the W65C22.
Refer to Table 1 for Register Select coding and a functional description. The W65C22S RS0-RS3 pins
have bus holding devices.
The RWB signal is generated by the microprocessor and is used to control the transfer of data between the
W65C22 and the microprocessor. When RWB is at a Logic 1 and the chip is selected, data is transferred
from the W65C22 to the microprocessor (Read operation). Conversely, when RWB is at logic 0, data is
transferred from the processor to the selected W65C22 register (Write operation). RWB must always be
preceded by a proper level on CS1, CS2B. The W65C22S RWB pin has a bus holding device.
VDD is the positive supply voltage and VSS is system logic ground .
3.8
3.9
3.10 Register Select (RS0-RS3)
3.11 RWB (Read/Write)
3.12 VDD and VSS
Phase 2 Internal Clock (PHI2)
Reset (RESB)
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