mf1s5001xdud NXP Semiconductors, mf1s5001xdud Datasheet
mf1s5001xdud
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mf1s5001xdud Summary of contents
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... Rev. 3.0 — 2 May 2011 196330 1. General description NXP Semiconductors has developed the MIFARE Classic MF1S50yyX to be used in a contactless smart card according to ISO/IEC 14443 Type A. The MIFARE Classic 1K MF1S50yyX IC is used in applications like public transport ticketing and can also be used for various other applications. ...
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... NXP Semiconductors 1.4 Delivery options • 7-byte UID, 4-byte NUID • bumped die on wafer • MOA4 and MOA8 contactless module 2. Features and benefits Contactless transmission of data and supply energy Operating frequency of 13.56 MHz Data integrity of 16-bit CRC, parity, bit coding, bit counting Typical ticketing transaction time of < ...
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... NXP Semiconductors 5. Ordering information Table 2. Ordering information Type number Package Name MF1S5001XDUD FFC Bump MF1S5001XDUF FFC Bump MF1S5000XDA4 MOA4 MF1S5000XDA8 MOA8 MF1S5031XDUD FFC Bump MF1S5031XDUF FFC Bump MF1S5030XDA4 MOA4 MF1S5030XDA8 MOA8 6. Block diagram Fig 2. MF1S50YYX Product data sheet COMPANY PUBLIC MIFARE Classic 1K - Mainstream contactless smart card IC Description 8 inch wafer, 120 μ ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning The pinning for the MF1S50yyXDAx is shown as an example in contactless module. For the contactless module MOA8, the pinning is analogous and not explicitly shown. Fig 3. Table 3. Pin LA LB MF1S50YYX Product data sheet COMPANY PUBLIC MIFARE Classic 1K - Mainstream contactless smart card IC ...
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... NXP Semiconductors 8. Functional description 8.1 Block description The MF1S50yyX chip consists EEPROM, RF interface and Digital Control Unit. Energy and data are transferred via an antenna consisting of a coil with a small number of turns which is directly connected to the MF1S50yyX. No further external components are necessary. Refer to the document • ...
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... NXP Semiconductors Remark: For the 4-byte non-unique ID product versions, the identifier retrieved from the card is not defined to be unique. For further information regarding handling of non-unique identifiers see 8.2.3 Select card With the select card command the reader selects one individual card for authentication and memory related operations ...
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... NXP Semiconductors 8.2.5 Memory operations After authentication any of the following operations may be performed: • Read block • Write block • Decrement: Decrements the contents of a block and stores the result in an internal data-register • Increment: Increments the contents of a block and stores the result in an internal data-register • ...
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... NXP Semiconductors 8.5 RF interface The RF-interface is according to the standard for contactless smart cards ISO/IEC 14443A. For operation, the carrier field from the reader always needs to be present (with short pauses when transmitting used for the power supply of the card. For both directions of data communication there is only one start bit at the beginning of each frame ...
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... NXP Semiconductors 8.6.1 Manufacturer block This is the first data block (block 0) of the first sector (sector 0). It contains the IC manufacturer data. This block is programmed and write protected in the production test. The manufacturer block is shown in UID version respectively. Fig 6. Fig 7. 8.6.2 Data blocks All sectors contain 3 blocks of 16 bytes for storing data (Sector 0 contains only two data blocks and the read-only manufacturer block) ...
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... NXP Semiconductors • Adr: Signifies a 1-byte address, which can be used to save the storage address of a block, when implementing a powerful backup management. The address byte is stored four times, twice inverted and non-inverted. During increment, decrement, restore and transfer operations the address remains unchanged. It can only be altered via a write command ...
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... NXP Semiconductors 8.7 Memory access Before any memory operation can be done, the card has to be selected and authenticated as described in depend on the key used during authentication and the access conditions stored in the associated sector trailer. Table 5. Operation Read Write Increment Decrement Transfer Restore ...
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... NXP Semiconductors 8.7.1 Access conditions The access conditions for every data block and sector trailer are defined by 3 bits, which are stored non-inverted and inverted in the sector trailer of the specified sector. The access bits control the rights of memory access using the secret keys A and B. The access conditions may be altered, provided one knows the relevant key and the current access condition allows this operation ...
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... NXP Semiconductors 8.7.2 Access conditions for the sector trailer Depending on the access bits for the sector trailer (block 3) the read/write access to the keys and the access bits is specified as ‘never’, ‘key A’, ‘key B’ or key A|B’ (key A or key B). On chip delivery the access conditions for the sector trailers and key A are predefined as transport configuration ...
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... NXP Semiconductors 8.7.3 Access conditions for data blocks Depending on the access bits for data blocks (blocks 0...2) the read/write access is specified as ‘never’, ‘key A’, ‘key B’ or ‘key A|B’ (key A or key B). The setting of the relevant access bits defines the application and the corresponding applicable commands. ...
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... NXP Semiconductors 9. Command overview The MIFARE Classic card activation follows the ISO/IEC 14443 Type A. After the MIFARE Classic card has been selected, it can either be deactivated using the ISO/IEC 14443 Halt command, or the MIFARE Classic commands can be performed. For more details about the card activation refer to 9 ...
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... NXP Semiconductors All timing can be measured according to ISO/IEC 14443-3 frame specification as shown for the Frame Delay Time in The frame delay time from PICC to PCD must be at least 87 μs. Fig 11. Frame Delay Time (from PCD to PICC) and T Remark: Due to the coding of commands, the measured timings usually excludes (a part of) the end of communication ...
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... NXP Semiconductors 9.4 ATQA and SAK responses For details on the type identification procedure please refer to The MF1S50yyX answers to a REQA or WUPA command with the ATQA value shown in Table 11 value shown in Table 11. Sales Type MF1S500yX MF1S503yX Table 12. Sales Type MF1S50yyX Remark: The ATQA coding in bits 7 and 8 indicate the UID size according to ISO/IEC 14443 independent from the settings of the UID usage ...
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... NXP Semiconductors 10. UID Options and Handling The MF1S50yyX product family offers two delivery options for the UID which is stored in block 0 of sector 0. • 7-byte UID • 4-byte NUID (Non-Unique ID) This section describes the MIFARE Classic MF1S50yyX operation when using one of the 2 UID options with respect to card selection, authentication and personalization ...
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... NXP Semiconductors Fig 12. Personalize UID Usage Table 13. Name Cmd Type CRC ACK, NAK Table 14. These times exclude the end of communication of the PCD. Personalize UID Usage 71 μs 10.1.2 Anti-collision and Selection Depending on the chosen personalization option there are certain possibilities to perform anti-collision and selection. To bring the MIFARE Classic into the ACTIVE state according to ISO/IEC 14443-3, the following sequences are available ...
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... NXP Semiconductors Table 15. UID Functionality UIDF0 UIDF1 UIDF2 UIDF3 10.1.3 Authentication During the authentication process, 4-byte of the UID are passed on to the MIFARE Classic Authenticate command of the contactless reader IC. Depending on the activation sequence, those 4-byte are chosen differently. Table 16. UID Functionality Sequence 1 ...
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... NXP Semiconductors 11. MIFARE Classic commands 11.1 MIFARE Authentication The MIFARE authentication is a 3-pass mutual authentication which needs two pairs of command-response. These two parts, MIFARE authentication part 1 and part 2 are shown in Figure Table 18 PICC ,,ACK'' PICC ,,NAK'' Time out Fig 13. MIFARE Authentication part 1 PICC `ACK` Fig 14 ...
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... NXP Semiconductors Table 18. These times exclude the end of communication of the PCD. Authentication part 1 Authentication part 2 Remark: The minimum required time between MIFARE Authentication part 1 and part 2 is the minimum required FDT according to Remark: The MIFARE authentication and encryption requires an MIFARE reader IC (e.g. ...
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... NXP Semiconductors 11.3 MIFARE Write The MIFARE Write requires a block address, and writes 16 bytes of data into the addressed MIFARE Classic 1K block. It needs two pairs of command-response. These two parts, MIFARE Write part 1 and part 2 are shown in Table 21. Table 22 Fig 16. MIFARE Write part 1 Fig 17. MIFARE Write part 2 Table 21 ...
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... NXP Semiconductors Table 22. These times exclude the end of communication of the PCD. Write part 1 Write part 2 Remark: The minimum required time between MIFARE Write part 1 and part 2 is the minimum required FDT according to 11.4 MIFARE Increment, Decrement and Restore The MIFARE Increment requires a source block address and an operand. It adds the operand to the value of the addressed block, and stores the result in a volatile memory ...
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... NXP Semiconductors (1) Increment, Decrement and Restore part 2 does not acknowledge Fig 19. MIFARE Increment, Decrement, Restore part 2 Table 23. Name Cmd Cmd Cmd Addr CRC Data NAK Table 24. These times exclude the end of communication of the PCD. Increment, Decrement, and Restore part 1 Increment, Decrement, and ...
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... NXP Semiconductors 11.5 MIFARE Transfer The MIFARE Transfer requires a destination block address, and writes the value stored in the volatile memory into one MIFARE Classic block. The command structure is shown in Figure 20 Table 26 Fig 20. MIFARE Transfer Table 25. Name Cmd Addr CRC NAK Table 26. ...
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... NXP Semiconductors 12. Limiting values Stresses above one or more of the limiting values may cause permanent damage to the device. Exposure to limiting values for extended periods may affect device reliability. Table 27. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol /pack ...
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... NXP Semiconductors 14. Wafer specification For more details on the wafer delivery forms see Table 29. Wafer diameter maximum diameter after foil expansion thickness flatness Potential Good Dies per Wafer (PGDW) Wafer backside material treatment roughness Chip dimensions step size gap between chips Passivation ...
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... NXP Semiconductors 14.2 Package outline For more details on the contactless modules MOA4 and MOA8 please refer to Ref. 8. PLLMC: plastic leadless module carrier package wide tape DIMENSIONS (mm are the original dimensions) (1) A UNIT D max. For unspecified dimensions see PLLMC-drawing given in the subpackage code. ...
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... NXP Semiconductors PLLMC: plastic leadless module carrier package wide tape Dimensions (1) Unit A D For unspecified dimensions see PLLMC-drawing given in the subpackage code. max 0.26 35.05 mm nom 35.00 min 34.95 Note 1. Total package thickness, exclusive punching burr. Outline version IEC SOT500 Fig 22. Package outline SOT500-4 ...
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... NXP Semiconductors 14.3 Bare die outline Fig 23. Bare die outline MF1S50yyX MF1S50YYX Product data sheet COMPANY PUBLIC MIFARE Classic 1K - Mainstream contactless smart card IC Chip Step Bump size LA, LB, VSS, TEST (1) typ. 19,0 min.5,0 240,8 LA 46,5 VSS 574,5 Y typ.659,0 X (1) the air gap and thus the step size may vary due to varying foil expansion (2) all dimensions in mm, pad locations measured from metal ring edge (see detail) All information provided in this document is subject to legal disclaimers ...
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... NXP Semiconductors 15. Abbreviations Table 30. Acronym ACK ATQA CRC CT EEPROM FDT FFC IC LCR LSB NAK NUID NV PCD PICC REQA RID RF RMS RNG SAK SECS-II TiW UID WUPA MF1S50YYX Product data sheet COMPANY PUBLIC MIFARE Classic 1K - Mainstream contactless smart card IC Abbreviations and symbols ...
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... NXP Semiconductors 16. References [1] MIFARE (Card) Coil Design Guide — Application note, BU-ID Document number 0117** [2] MIFARE Type Identification Procedure — Application note, BU-ID Document number 0184** [3] ISO/IEC 14443-2 — 2001 [4] ISO/IEC 14443-3 — 2001 [5] MIFARE & I-CODE CL RC632 Multiple protocol contactless reader IC — ...
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... NXP Semiconductors 17. Revision history Table 31. Revision history Document ID Release date MF1S50YYX v.3.0 20110502 • Modifications: General update MF1S50YYX v.2.0 20101122 MF1S50YYX Product data sheet COMPANY PUBLIC MIFARE Classic 1K - Mainstream contactless smart card IC Data sheet status Product data sheet Preliminary data sheet All information provided in this document is subject to legal disclaimers. ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die ...
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... NXP Semiconductors 20. Tables Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .2 Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 3. Pin allocation table . . . . . . . . . . . . . . . . . . . . . . .4 Table 4. Value block format example . . . . . . . . . . . . . . .10 Table 5. Memory operations . . . . . . . . . . . . . . . . . . . . . . 11 Table 6. Access conditions . . . . . . . . . . . . . . . . . . . . . . .12 Table 7. Access conditions for the sector trailer . . . . . .13 Table 8. Access conditions for data blocks .14 Table 9. Command overview . . . . . . . . . . . . . . . . . . . . .15 Table 10 ...
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... NXP Semiconductors 21. Figures Fig 1. MIFARE card reader . . . . . . . . . . . . . . . . . . . . . . .1 Fig 2. Block diagram of MF1S50yyX . . . . . . . . . . . . . . . .3 Fig 3. Pin configuration for SOT500-2 (MOA4 Fig 4. Three pass authentication . . . . . . . . . . . . . . . . . . .6 Fig 5. Memory organization . . . . . . . . . . . . . . . . . . . . . . .8 Fig 6. Manufacturer block for MF1S503yX with 4-byte NUID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Fig 7. Manufacturer block for MF1S500yX with 7-byte UID Fig 8. ...
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... NXP Semiconductors 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Anticollision 1.2 Simple integration and user convenience 1.3 Security 1.4 Delivery options . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Functional description . . . . . . . . . . . . . . . . . . . 5 8.1 Block description . . . . . . . . . . . . . . . . . . . . . . . 5 8.2 Communication principle . . . . . . . . . . . . . . . . . 5 8 ...