A43L8316AV AMICC [AMIC Technology], A43L8316AV Datasheet - Page 11

• Manufacturer Part Number: A43L8316AV
• Description: 128K X 16 Bit X 2 Banks Synchronous DRAM
• Manufacturer: AMICC [AMIC Technology]

Mode Register Filed Table to Program Modes
Register Programmed with MRS
Power Up Sequence
1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200 s.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.
The device is now ready for normal operation.
Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.
(September, 2003, Version 1.0)
BA
A8
0
1
0
0
1
1
Address
Function
2. If BA is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
3. The full column burst (256bit) is available only at Sequential mode of burst type.
A7
Write Burst Length
0
1
0
1
(Note 1)
Test Mode
Mode Register Set
Single Bit
Length
Burst
RFU
Vendor
BA
Type
Only
Use
A8
(Note 2)
A6
TM
0
0
0
0
1
1
1
1
A7
A5
0
0
1
1
0
0
1
1
CAS Latency
A4
0
1
0
1
0
1
0
1
A6
Reserved
Reserved
Reserved
Reserved
Reserved
Latency
2
3
-
CAS Latency
10
A5
A3
0
1
Burst Type
Sequential
Interleave
A4
Type
A3
A2
0
0
0
0
1
1
1
1
AMIC Technology, Corp.
A1
BT
0
0
1
1
0
0
1
1
A0
A2
0
1
0
1
0
1
0
1
Burst Length
Reserved
Reserved
Reserved
256(Full)
BT=0
A43L8316A
1
2
4
8
A1
Burst Length
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BT=1
(Note 3)
4
8
A0