P102-03SC PLL [PhaseLink Corporation], P102-03SC Datasheet

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P102-03SC

Manufacturer Part Number
P102-03SC
Description
Low Skew Output Buffer
Manufacturer
PLL [PhaseLink Corporation]
Datasheet
FEATURES
DESCRIPTION
The PLL102-03 is a high performance, low skew, low
jitter zero delay buffer designed to distribute high
speed clocks and is available in an 8-pin SOIC pack-
age. It has four outputs that are synchronized with the
input. The synchronization is established via CLKOUT
feed back to the input of the PLL. Since the skew be-
tween the input and output is less than ±350 ps, the
device acts as a zero delay buffer.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 02/23/06 Page 1
Frequency range 75 ~ 180MHz.
Internal phase locked loop will allow spread spec-
trum modulation on reference clock to pass to the
outputs (up to 100kHz SST modulation).
Zero input - output delay.
Less than 700 ps device - device skew.
Less than 250 ps skew between outputs.
Less than 150 ps cycle - cycle jitter.
Output Enable function tri-state outputs.
3.3V operation.
Available in 8-Pin 150mil SOIC
REF
GREEN
package.
PLL
PIN CONFIGURATION
Remark
If REF clock is stopped for more than 10us after it has already been
provided to the chip, and after power-up, the output clocks will
disappear. In that instance, a full power-up reset is required in order
to reactivate the output clocks.
CLK2
CLK1
GND
REF
Low Skew Output Buffer
CLKOUT
1
2
3
4
CLK1
CLK2
CLK3
CLK4
8
7
6
5
PLL102-03
CLKOUT
CLK4
VDD
CLK3

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P102-03SC Summary of contents

Page 1

FEATURES • Frequency range 75 ~ 180MHz. • Internal phase locked loop will allow spread spec- trum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation). • Zero input - output delay. • Less than ...

Page 2

PIN DESCRIPTIONS Name Number REF 1 1 CLK2 2 2 CLK1 3 2 GND 4 CLK3 5 2 VDD 6 CLK4 7 2 CLKOUT 8 2 Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. ELECTRICAL SPECIFICATIONS 1. Absolute ...

Page 3

Switching Characteristics PARAMETERS SYMBOL Output Frequency Duty Cycle ( t2 ÷ Duty Cycle ( t2 ÷ Rise Time Fall Time Output to Output Skew T Delay, REF Rising Edge to T CLKOUT Rising Edge Device ...

Page 4

SWITCHING WAVE FORMS All Outputs Rise/Fall Time 2.0V 0.8V Output t r Input to Output Propagation Delay Input Output T delay Device to Device Skew Device1 CLKOUT Device2 CLKOUT 47745 Fremont ...

Page 5

Output-Output Skew The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are ...

Page 6

... BSC 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL102- Marking P102-03SC P102-03SC P102-03SCL P102-03SCL PLL102-03 Low Skew Output Buffer NONE= TUBE R=TAPE AND REEL NONE=NORMAL PACKAGE L=GREEN PACKAGE ...

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