P650-01XC PLL [PhaseLink Corporation], P650-01XC Datasheet

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P650-01XC

Manufacturer Part Number
P650-01XC
Description
Low EMI Network LAN Clock
Manufacturer
PLL [PhaseLink Corporation]
Datasheet
FEATURES
DESCRIPTION
The PLL650-01 is a low cost, low jitter, high
performance clock synthesizer. With PhaseLink’s
proprietary analog Phase Locked Loop techniques,
the chip accepts 25.0MHz from a crystal or a refer-
ence clock, and produces multiple outputs clocks for
network chips, PCI devices, SDRAM, and ASICs.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1
Full CMOS output swing with 25 mA output drive
capability at TTL levels.
Advanced, low power, sub-micron CMOS
process.
25.0MHz fundamental crystal or reference clock
signal.
Six output clocks with selectable frequencies.
SDRAM frequencies of 67,83,100, and 133MHz.
Spread Spectrum Technology selectable for EMI
Reduction from ±0.25% to ±0.5% center.
Buffered crystal reference output.
Ideal for Network switches.
3.3V operation.
Available in 150mil 20-Pin SSOP.
XOUT
FS (0:4)
CS (0:1)
XIN
XTAL
OSC
Control
Logic
PIN CONFIGURATION
Note: ^: 100kΩ internal pull-up. *: Bi-directional pin. The value of
CS1 is latched upon power-up. When no external pull-down re-
sistor is connected to the pin, the internal pull-up results in a
default high value for CS1. An external 10kΩ pull-down resis-
tor is recommended to set CS1 to low.
Low EMI Network LAN Clock
CLKC1
CLKC2
CLKB2
CLKB1
OE
XOUT
GND
VDD
FS0
FS1
XIN
1
2
3
4
5
6
7
8
9
10
PLL650-01
20
19
18
17
16
15
14
13
12
11
REFOUT
CLKA1
CLKA2
CLKB1
CLKB2
CLKC1
CLKC2
FS3
FS2
REF/CS1*^
CLKA1
VDD
OE^
GND
CLKA2
FS4
CS0

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P650-01XC Summary of contents

Page 1

FEATURES • Full CMOS output swing with 25 mA output drive capability at TTL levels. • Advanced, low power, sub-micron CMOS process. • 25.0MHz fundamental crystal or reference clock signal. • Six output clocks with selectable frequencies. • SDRAM frequencies ...

Page 2

PIN DESCRIPTIONS Name Number CLKA1 17 CLKA2 13 CLKB1 10 CLKB2 9 CLKC1 7 CLKC2 8 XIN 3 XOUT 2 FS2 19 FS3 20 CS0 11 FS0 1 FS1 5 FS4 REF/CS1 18 VDD 4,16 GND 6,14 ...

Page 3

FREQUENCY (MHz) SELECTION TABLE (For a 25MHz Crystal or Clock Input) FS0 FS1 FS2 FS3 ...

Page 4

FUNCTIONAL DESCRIPTION Selectable spread spectrum and output frequencies The PLL650-01 provides selectable spread spectrum modulation and selectable output frequencies, as well as an “output enable” selection input (pin 15). Selection is made by connecting specific pins to a logical “zero” ...

Page 5

APPLICATION DIAGRAM FOR SETTING CS1 (PIN 18) Latched Input NOTE: Rup=100kΩ starts from while RB starts from Electrical Specifications 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc ...

Page 6

AC Specifications PARAMETERS Input Frequency Output Rise Time Output Fall Time Duty Cycle Max. Absolute Jitter Max. Jitter, cycle to cycle 3. DC Specifications PARAMETERS SYMBOL Operating Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low ...

Page 7

... BSC 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL650- Marking P650-01XC P650-01XC PLL650-01 Low EMI Network LAN Clock TEMPERATURE C=COMMERCIAL I=INDUSTRAL PACKAGE TYPE ...

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