PLL102-108XC PLL [PhaseLink Corporation], PLL102-108XC Datasheet
PLL102-108XC
Related parts for PLL102-108XC
PLL102-108XC Summary of contents
Page 1
... Support 2-wire I2C serial bus interface. 2.5V Operating Voltage. Available in 48-Pin 300mil SSOP. DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK_INT ...
Page 2
... PLL for I synchronization with CLK_INT to eliminate phase error. B Serial data input for serial interface port. I CLK_INC CLKT PLL102-108 Description OUTPUTS CLKC FB_OUTT Rev 03/29/02 Page 2 PLL State On ...
Page 3
... Default Description 1 CLKT7, CLKC7 (1= active, 0=inactive) 1 CLKT6, CLKC6 (1= active, 0=inactive) 1 CLKT5, CLKC5 (1= active, 0=inactive) 1 CLKT4, CLKC4 (1= active, 0=inactive) 1 CLKT3, CLKC3 (1= active, 0=inactive) 1 CLKT2, CLKC2 (1= active, 0=inactive) 1 CLKT1, CLKC1 (1= active, 0=inactive) 1 CLKT0, CLKC0 (1= active, 0=inactive) PLL102-108 Rev 03/29/02 Page 3 ...
Page 4
... Table These three bits will adjust timing of DDRD signals (CLK6) either 1 positive or negative delay up to +400ps or –300ps with 100ps per step. (see Table 1) 1 PLL102-108 Setting applies to the following out- puts: 1. FB_OUTT Description Description Rev 03/29/02 Page 4 ...
Page 5
... These four bits will program the propagation delay from CLK_INT 0 to the input of PLL within the range between 0ps and 2.5ns with 0 170ps step size. (see Table 2) 0 +2,550 ps +2,380 ps +2,210 ps +2,040 ps +1,870 ps +1,700 ps +1,530 ps +1,360 ps +1,190 ps +1,020 ps +850 ps +680 ps +510 ps +340 ps +170 ps Default PLL102-108 Description Rev 03/29/02 Page 5 ...
Page 6
... CLK9 output clocks (see Table 3). 1 Default 1 Reserved. 1 Reserved. 0 These three bits will program drive strength for CLK2, CLK3 and 1 CLK4 output clocks (see Table 3 These three bits will program drive strength for CLK6 output clock 1 (see Table 3). 1 PLL102-108 Description Description Rev 03/29/02 Page 6 ...
Page 7
... Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Programmable DDR Zero Delay Clock Driver Default 1 Reserved. 1 Reserved. 1 Reserved. 1 Reserved. 1 Reserved. 0 These three bits will program drive strength for FBOUTT output 1 clock (see Table 3). 1 PLL102-108 Description Rev 03/29/02 Page 7 ...
Page 8
... DDPD I VDD=2.7V, V =VDD or GND OZ OUT I = -18mA VDD or GND VDD or GND OUT O VDD = Min to Max VDD = 2.3V -12mA OH VDD = Min to Max VDD = 2.3V 12mA PLL102-108 MIN. MAX. - 3 0 0 -65 150 0.7 MIN. TYP. 250 -1mA VDD-0 ...
Page 9
... T cyc-cyc 100/133/200/266MHz (phase error) All differential input and output terminals are terminated with T oskew 120 16pF T pskew 66MHz to 100MHz D T 101MHz to 266MHz t t Load = 120 16pF r, f PLL102-108 MIN. TYP. MAX. 2.3 2.5 2.7 2.3 2.5 2 MIN. MAX. 66 266 40 60 0.1 MIN. TYP. ...
Page 10
... MIN (0.203 - 0.406) 48PIN SSOP 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL102-108 X C PLL102-108 0.025 0.635 0.088 - 0.096 (2.235 - 2.438) 0.097 - 0.104 (2.464 - 2.642) TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE ...