MB82D01181E-60LPBN FUJITSU [Fujitsu Component Limited.], MB82D01181E-60LPBN Datasheet
MB82D01181E-60LPBN
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MB82D01181E-60LPBN Summary of contents
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... DESCRIPTION MB82D01181E is a Fast Cycle Random Access Memory (FCRAM) with asynchronous Static Random Access Memory (SRAM) interface containing 16,777,216 storages accessible in a 16-bit format. MB82D01181E is suited for mobile applications such as Cellular Handset and PDA. Note: FCRAM is a trademark of Fujitsu Limited, Japan. ...
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... MB82D01181E -60L PIN ASSIGNMENT PIN DESCRIPTION Pin Name Address Input 19 0 CE1 Chip Enable (Low Active) CE2 Chip Enable (High Active) WE Write Enable (Low Active) OE Output Enable (Low Active) LB Lower Byte Control (Low Active) UB Upper Byte Control (Low Active ...
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... Power CE2 Control CE1 MB82D01181E Memory Address Row Latch & Decoder Buffer 16,777,216 bits Input Data Sense / I/O Latch & Buffer Control Column Decoder Address Latch & Timing Control -60L Cell Array ...
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... MB82D01181E -60L FUNCTION TRUTH TABLE Mode CE2 CE1 Standby (Deselect Output Disable* No Read Read (Upper Byte) Read (Lower Byte) H Read (Word Write Write (Upper Byte) Write (Lower Byte) Write (Word) Power Down * Note : either Output disable mode should not be kept longer than 1 µs. ...
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... V 2.3 DD (23 (31 (23, 27) DD −0 and V on identical device (31) DD (27) DD (23) varied according to V supply voltage MB82D01181E -60L Rating Unit Min Max +3.6 V +3.6 V +3.6 V −50 +50 mA −55 +125 °C Value Unit Max 3.5 V 3 ...
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... MB82D01181E -60L PIN CAPACITANCE Parameter Address Input Capacitance Control Input Capacitance Data Input/Output Capacitance DC CHARACTERISTICS Parameter Symbol Input Leakage Current Output Leakage Current V Output High Voltage Level V V Output Low Voltage Level V Power Down Current DD V Standby Current Active Current ...
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... The output load 5 pF without any other load Applicable when CE1 is kept at Low (Min) must be satisfied the actual value shorter than specified minimum value, the actual t WHOL longer by the amount of subtracting actual value from specified minimum value. MB82D01181E Value Symbol Min Max t 70 1000 RC ⎯ ...
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... MB82D01181E -60L (2) Write Operation Parameter Write Cycle Time Address Setup Time CE1 Write Pulse Width WE Write Pulse Width LB, UB Write Pulse Width LB, UB Byte Mask Setup Time LB, UB Byte Mask Hold Time Write Recovery Time CE1 High Pulse Width WE High Pulse Width ...
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... AC testing shown in below. If actual t T violate AC specifications of some timing parameters. (5) AC Test Conditions Parameter Input High Level Input Low level Input Timing Measurement Level Input Transition Time (6) AC Measurement Output Load Circuit MB82D01181E Symbol Min t 10 CSP t 80 C2LP t 300 CHH t 0 CHS ...
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... MB82D01181E -60L TIMING DIAGRAM 1. READ Timing 1 (Basic Timing) Address t ASC CE1 OE LB (Output) Note : This timing diagram assumes CE2 = “H” and WE = “H”. 2. READ Timing 2 (OE & Address Access) Address CE1 Low t ASO OE LB (Output) Note : This timing diagram assumes CE2 = “H” and WE = “H”. ...
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... Note : This timing diagram assumes CE2 = “H” Address Valid BHZ t OH Valid Data Output t BLZ Valid Data Output t WC Address Valid Valid Data Input MB82D01181E -60L BHZ t t BLZ OH t BHZ WHP t ...
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... MB82D01181E -60L 5. WRITE Timing 2 (WE Control) Address t OHAH CE1 Low LB OES OE t OHZ DQ (Input) Note : This timing diagram assumes CE2 = “H”. 6. WRITE Timing 3-1 (WE, LB, UB Byte Write Control) Address CE1 Low (Input) ...
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... Valid Data Input t WC Address Valid t WHP Valid Data Input MB82D01181E -60L t WC Address Valid Valid Data Input t WC Address Valid ...
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... MB82D01181E -60L 9. WRITE Timing 3-4 (WE, LB, UB Byte Write Control) Address CE1 Low (Input (Input) Note : This timing diagram assumes CE2 = “H” and OE = “H”. 10. READ/WRITE Timing 1-1 (CE1 Control) Address t t CHAH AS CE1 t CP ...
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... Write Data Input t WC Write Address Read Address ASO t WHOL OLZ Write Data Input MB82D01181E -60L t RC Read Address CHAH OLZ OH Read Data Output OHAH OHZ t OH ...
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... MB82D01181E -60L 13. READ/WRITE Timing 3 (OE, WE, LB, UB Control) Address CE1 t OHAH Low WE t OES UB BHZ Read Data Output Note : This timing diagram assumes CE2 = “H”. CE1 can be tied to Low for WE and OE controlled operation Write Address ...
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... Note : t specifies after V reaches specified minimum level and applicable to both CE1 and CE2. CHH DD If transition time of V (from applied. t CHS t C2LH (Min CHH (Min) Min) is longer than 100 ms, POWER-UP Timing#1 must be DD MB82D01181E -60L t CHH 17 ...
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... MB82D01181E -60L 16. POWER DOWN Entry and Exit Timing CE1 CE2 t CSP DQ Power Down Entry Note : This Power Down mode can be also used as a reset timing if POWER-UP timing could not be satisfied. 17. Standby Entry Timing after Read or Write CE1 OE WE Active (Read) Note : Both t and t define the earliest entry timing for Standby mode ...
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... BONDING PAD INFORMATION Please contact local FUJITSU representative for pad layout and pad coordinate information. ORDERING INFORMATION Part No. MB82D01181E-60LWT MB82D01181E-60LPBN MB82D01181E Shipping Form/Package Wafer 48-pin plastic FBGA (BGA-48P-M18) -60L Remarks SRAM compatible FBGA package = 60 ns Max ...
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... MB82D01181E -60L PACKAGE DIMENSION 48-pin plastic FBGA (BGA-48P-M18) 48-pin plastic FBGA (BGA-48P-M18) 9.00 ± 0.10(.354 ± .004) INDEX AREA 0.20(.008 0.10(.004) S 2001 FUJITSU LIMITED B48018S-c-1 Ball pitch Package width × package length Lead shape Sealing method Mounting height Weight +0.15 1.05 –0.10 (Mounting height) + ...
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... MB82D01181E -60L FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device ...