MB82D01181E-60LPBN FUJITSU [Fujitsu Component Limited.], MB82D01181E-60LPBN Datasheet - Page 8

• Manufacturer Part Number: MB82D01181E-60LPBN
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

8
MB82D01181E
(2) Write Operation
*1 : Maximum value is applicable if CE1 is kept at Low without any address change.
*2 : Minimum value must be equal or greater than the sum of write pulse width (t
*3 : Write pulse width is defined from High to Low transition of CE1, WE, LB or UB, whichever occurs last.
*4 : Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1 or WE
*5 : Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1 or WE
*6 : Write recovery time is defined from Low to High transition of CE1, WE, LB or UB, whichever occurs first.
*7 : If OE is Low after minimum t
*8 : If OE is Low after new address input, read cycle is initiated. In other words, OE must be brought to High at the
Note : AC Characteristics are measured after following POWER-UP timing.
Write Cycle Time
Address Setup Time
CE1 Write Pulse Width
WE Write Pulse Width
LB, UB Write Pulse Width
LB, UB Byte Mask Setup Time
LB, UB Byte Mask Hold Time
Write Recovery Time
CE1 High Pulse Width
WE High Pulse Width
LB, UB High Pulse Width
Data Setup Time
Data Hold Time
OE High to Address Setup Time for Write
OE High to CE1 Low Setup Time for Write
LB and UB Write Pulse Overlap
whichever occurs first.
time (t
whichever occurs last.
after CE1 is brought to Low.
same time or before new address valid.
WR
) .
Parameter
-60L
OHCL
, read cycle is initiated. In other words, OE must be brought to High within 5 ns
Symbol
t
t
t
t
t
OHCL
t
t
t
t
t
t
t
WHP
t
t
BWO
t
t
OES
BHP
WC
CW
WR
WP
BW
DH
AS
BS
BH
CP
DS
Min
70
45
45
45
−5
−5
10
10
10
15
−5
30
0
0
0
0
Value
CW
1000
1000
1000
Max
, t
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
WP
or t
BW
) and write recovery
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*1, *2
*2
*3
*3
*3
*4
*5
*6
*8
*7
Notes