IDT7024L IDT [Integrated Device Technology], IDT7024L Datasheet - Page 10

• Manufacturer Part Number: IDT7024L
• Description: HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
• Manufacturer: IDT [Integrated Device Technology]

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/
TIMING WAVEFORM OF WRITE CYCLE NO. 2,
NOTES:
1. R/
2. A write occurs during the overlap (t
3. t
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
6. Timing depends on which enable signal is asserted last,
7. This parameter is guaranted by device characterization, but is not production tested. Transition is measured +/- 500mV steady state with the Output Test
8. If
9. To access RAM,
ADDRESS
ADDRESS
CE
DATA
CE
Load (Figure 2).
DATA
UB
to be placed on the bus for the required t
can be as short as the specified t
met for either condition.
WR
UB
OE
W
DATA
or
or
is measured from the earlier of
or
or
or
CE
R/
is Low during R/
SEM
IN
R/
SEM
OUT
LB
CE
OE
LB
W
W
or
IN
or
(9)
SEM
(9)
(9)
(9)
UB
CE
Low transition occurs simultaneously with or after the R/
&
LB
= V
W
must be High during all address transitions.
IL
controlled write cycle, the write pulse width must be the larger of t
,
UB
t
AS
t
or
(6)
AS
WP .
LB
(6)
EW
CE
(4)
or t
= V
or R/
WP
DW
IL
W
, and
) of a Low
. If
(or
OE
SEM
SEM
t
WZ
is High during an R/
UB
(7)
t
or R/
= V
t
AW
CE
AW
t
t
or
WC
WC
IH
, R/
W
. To access Semaphore,
LB
t
) going High to the end-of-write cycle.
EW
t
W
WP
and a Low
,
(2)
UB,
(2)
6.15
or
CE CE CE CE CE
W
LB
W
W W W W W
controlled write cycle, this requirement does not apply and the write pulse
,
CE
.
Low transition, the outputs remain in the High-impedance state.
UB UB
UB UB
UB
CONTROLLED TIMING
t
and a Low R/
t
DW
DW
,
LB LB LB LB LB
CE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CONTROLLED TIMING
WP
= V
t
WR
W
for (t
IH
(3)
for memory array writing cycle.
or
WZ
t
t
DH
UB
t
DH
WR
+ t
t
OW
DW
&
(3)
LB
) to allow the I/O drivers to turn off and data
= V
IH
, and
(1,5,8)
t
HZ
SEM
(7)
(4)
(1,5)
= V
IL
. t
EW
must be
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