IDT7024L IDT [Integrated Device Technology], IDT7024L Datasheet - Page 16

• Manufacturer Part Number: IDT7024L
• Description: HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
• Manufacturer: IDT [Integrated Device Technology]

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
NOTES:
1. Pins
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable
3. Writes to the left port are internally ignored when
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7024.
2. There are eight semaphore flags written to via I/O
TRUTH TABLE IV —
ADDRESS BUSY ARBITRATION
TRUTH TABLE V — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE
FUNCTIONAL DESCRIPTION
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT7024 has an
automatic power down feature controlled by
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(
memory array is permitted.
INTERRUPTS
location (mail box or message center) is assigned to each port.
The left port interrupt flag (
writes to memory location FFE (HEX), where a write is defined
as the
the interrupt by access address location FFE access when
CE
interrupt flag (
CE
CE CE CE CE CE
IDT7024 are push pull, not open drain outputs. On slaves, the
after the address and enable inputs of this port. If tAPS is not met, either
simultaneously.
internally ignored when
No Action
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
H
X
X
L
The IDT7024 provides two ports with separate control,
If the user chooses to use the interrupt function, a memory
R
L
High). When a port is enabled, access to the entire
=
BUSY
CE
OE
CE CE CE CE CE
X
X
H
L
R =
= R/
Inputs
R
L
and
V
Functions
NO MATCH
W
IL,
A
INT
A
MATCH
MATCH
MATCH
BUSY
0R
0L
R/
= V
-A
-A
R
W
) is asserted when the left port writes to
IL
11L
11R
R
is a "don't care". Likewise, the right port
BUSY
per the Truth Table. The left port clears
are both outputs when the part is configured as a master. Both are inputs when configured as a slave.
BUSY
BUSY
BUSY
BUSY
BUSY
INT
R
outputs are driving low regardless of actual logic level on the pin.
(2)
H
H
H
L
) is asserted when the right port
L
Outputs
(1)
BUSY
BUSY
BUSY
BUSY
BUSY
D
(2)
H
H
H
0
- D
R
BUSY
0
(1)
1
0
0
1
1
0
1
1
1
0
1
and read from all the I/O's (I/O
15
Normal
Normal
Normal
Write Inhibit
Left
L
CE
outputs are driving low regardless of actual logic level on the pin. Writes to the right port are
Function
. The
2740 tbl 16
BUSY
D
0
- D
(3)
CE
asserted input internally inhibits write.
6.15
15
BUSY
1
1
1
0
0
1
1
0
1
1
1
Right
memory location FFF (HEX) and to clear the interrupt flag
(
The message (16 bits) at FFE or FFF is user-defined, since it
is an addressable SRAM location. If the interrupt function is
not used, address locations FFE and FFF are not used as mail
boxes, but as part of the random access memory. Refer to
Truth Table for the interrupt operation.
BUSY LOGIC
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is “Busy”. The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
INT
L
Busy Logic provides a hardware indication that both ports
The use of busy logic is not required or desirable for all
or
R
), the right port must access the memory location FFF.
0
BUSY
-I/O
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
15
R
MILITARY AND COMMERCIAL TEMPERATURE RANGES
). These eight semaphores are addressed by A
= Low will result.
BUSY
Status
L
and
BUSY
(1,2)
R
BUSY
outputs cannot be low
X
outputs on the
0
- A
2740 tbl 19
2
.
16