ADF4110 Analog Devices, ADF4110 Datasheet
ADF4110
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ADF4110 Summary of contents
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... AGND RF PLL Frequency Synthesizers ADF4110/ADF4111/ADF4112/ADF4113 GENERAL DESCRIPTION The ADF4110 family of frequency synthesizers can be used to implement local oscillators in the upconversion and down- conversion sections of wireless receivers and transmitters. They consist of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, programmable A and B counters and a dual-modulus prescaler (P ...
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... Output High Voltage Output Low Voltage OL POWER SUPPLIES ( ADF4110 ADF4111 ADF4112 ADF4113 I P Low Power Sleep Mode ≤ V ≤ 6.0 V; AGND = DGND = CPGND = Version B Chips Unit 80/550 80/550 MHz min/max 50/550 50/550 MHz min/max ...
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... ADF4110 = 540 MHz 540 MHz 2700; Loop B kHz 900 MHz 4500; Loop B kHz 836 MHz 27867; Loop B kHz 1750 MHz 8750; Loop B kHz. ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumu- late on the human body and test equipment and can discharge without detection. Although the ADF4110/ADF4111/ADF4112/ADF4113 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... and an equivalent input resis- DD must be the same value systems where V DD CHIP SCALE PACKAGE 1 15 CPGND MUXOUT ADF4110 ADF4111 14 AGND 2 LE ADF4112 AGND 3 13 DATA ADF4113 TOP VIEW CLK ...
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... ADF4110/ADF4111/ADF4112/ADF4113 FREQ-UNIT PARAM-TYPE DATA-FORMAT KEYWORD GHz FREQ MAGS11 ANGS11 FREQ MAGS11 0.05 0.89207 –2.0571 1.05 0.9512 0.10 0.8886 –4.4427 1.10 0.93458 0.15 0.89022 –6.3212 1.15 0.94782 0.20 0.96323 –2.1393 1.20 0.96875 0.25 0.90566 –12.13 1.25 0.92216 0.30 0.90307 –13.52 1.30 0.93755 0.35 0.89318 –15.746 1.35 0.96178 0.40 0.89806 –18.056 1 ...
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... RES. BANDWIDTH = 10kHz –30 VIDEO BANDWIDTH = 10kHz SWEEP = 477ms –40 AVERAGES = 10 –50 –60 –70 –80 –75.2dBc/Hz –90 –100 –400Hz –200Hz 1750MHz +200Hz ADF4110/ADF4111/ADF4112/ADF4113 10dB/DIVISION –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 100Hz FREQUENCY OFFSET FROM 1750MHz CARRIER +400kHz 0 REFERENCE – ...
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... ADF4110/ADF4111/ADF4112/ADF4113 10dB/DIVISION –40dBc/Hz –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 100Hz FREQUENCY OFFSET FROM 3100MHz CARRIER 0 V REFERENCE DD – 5mA LEVEL = –17.2dBm CP PFD FREQUENCY = 1MHz –20 LOOP BANDWIDTH = 100kHz –30 RES. BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz – ...
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... TEMPERATURE – –1 –2 –3 –4 –5 –6 0 0.5 ADF4110/ADF4111/ADF4112/ADF4113 ADF4110 ADF4111 100 3 2.5 P 2.0 1.5 1.0 0 100 SETTING : 5mA CP 1 1 ...
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... ADF4110/ADF4111/ADF4112/ADF4113 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 2. SW1 and SW2 are normally-closed switches. SW3 is normally-open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REF on power-down. POWER-DOWN ...
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... R COUNTER OUTPUT N COUNTER OUTPUT CPGND INPUT SHIFT REGISTER The ADF4110 family digital section includes a 24-bit input shift register, a 14-bit R counter and a 19-bit N counter, comprising a 6-bit A counter and a 13-bit B counter. Data is clocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB fi ...
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... SETTING VALUE 2 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 Table II. ADF4110 Family Latch Summary REFERENCE COUNTER LATCH 14-BIT REFERENCE COUNTER, R DB16 DB15 DB14 DB13 DB12 DB11 DB10 R14 R13 R12 R11 R10 R9 N COUNTER LATCH ...
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... OUTPUT OF PRESCALER IS RESYNCHRONIZED WITH NONDELAYED VERSION OF RF INPUT 1 0 NORMAL OPERATION 1 1 OUTPUT OF PRESCALER IS RESYNCHRONIZED WITH DELAYED VERSION OF RF INPUT ADF4110/ADF4111/ADF4112/ADF4113 Table III. Reference Counter Latch Map 14-BIT REFERENCE COUNTER DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 R14 R13 ...
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... ADF4110/ADF4111/ADF4112/ADF4113 RESERVED DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB23 DB22 B13 B12 B11 B10 X = DON'T CARE B13 B12 • • • • • • (FUNCTION LATCH) CP GAIN FASTLOCK ENABLE* ...
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... NORMAL OPERATION ASYNCHRONOUS POWER-DOWN SYNCHRONOUS POWER-DOWN P2 P1 PRESCALER VALUE 16/ 32/ 64/65 ADF4110/ADF4111/ADF4112/ADF4113 Table V. Function Latch Map TIMER COUNTER CONTROL DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 TC4 TC3 TC2 TC1 PHASE DETECTOR F2 POLARITY 0 NEGATIVE ...
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... ADF4110/ADF4111/ADF4112/ADF4113 CURRENT CURRENT PRESCALER SETTTING SETTTING VALUE 2 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 PIN ...
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... N counter resumes counting in “close” alignment with the R counter. (The maximum error is one prescaler cycle.) Power-Down DB3 (PD1) and DB21 (PD2) on the ADF4110 family, provide programmable power-down modes. They are enabled by the CE pin. When the CE pin is low, the device is immediately disabled regardless of the states of PD2, PD1 ...
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... Typically improve- ment is seen in the ADF4113. The lower bandwidth devices can show an even greater improvement. For example, the ADF4110 phase noise is typically improved when SYNC is enabled. With DLY = “1,” the prescaler output is resynchronized with a delayed version of the RF input ...
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... In this example, the loop filter was designed so that the overall phase margin for the system would be 45 degrees. Other PLL system specifications are: 1000pF 1000pF FREF 4.7k ADF4110/ADF4111/ADF4112/ADF4113 MHz/V V Loop Bandwidth = 20 kHz F = 200 kHz REF ...
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... V-OUT DAC SPI COMPATIBLE SERIAL BUS USING A D/A CONVERTER TO DRIVE R You can use a D/A converter to drive the R ADF4110 family and thus increase the level of control over the charge pump current I . This can be advantageous in wideband CP applications where the sensitivity of the VCO varies over the tuning range ...
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... SET ADF4113 CE 14 CLK MUXOUT DATA LE 100pF ADF4110/ADF4111/ADF4112/ADF4113 S IN ADG701 LOOP CP FILTER VCO 1 GND 4.7k 100pF 100pF DECOUPLING CAPACITORS AND INTERFACE SIGNALS HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY. 20V ...
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... ADF4110/ADF4111/ADF4112/ADF4113 DIRECT CONVERSION MODULATOR In some applications a direct conversion architecture can be used in base station transmitters. Figure 11 shows the combination available from ADI to implement this solution. The circuit diagram shows the AD9761 being used with the AD8346. The use of dual integrated DACs such as the AD9761 with specified ± ...
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... The microconverter is set up for SPI Master Mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4110 family needs a 24-bit word. This is accomplished by writing three 8-bit bytes from the microconverter to the device. When the third byte has been written the LE input should be brought high to complete the transfer ...
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... ADF4110/ADF4111/ADF4112/ADF4113 PIN 1 INDICATOR 0.039 (1.00) MAX 0.033 (0.85) NOM SEATING ADF4110/ADF4111/ADF4112/ADF4113–Revision History Location Changed Data Sheet from REV REV. A. Changes to DC Specifications in B Version, B Chips, Unit and Test Conditions/Comments columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Change Function text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 IN Changes to Figure New graph added— ...