IDT70V38L15PFI IDT [Integrated Device Technology], IDT70V38L15PFI Datasheet - Page 11

• Manufacturer Part Number: IDT70V38L15PFI
• Description: HIGH-SPEED 3.3V 64K x 18 DUAL-PORT STATIC RAM
• Manufacturer: IDT [Integrated Device Technology]

Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V
DATA
NOTES:
1. To ensure that the earlier of the two ports wins. t
2. CE
3. OE = V
4. If M/S = V
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/S = V
NOTES:
1. t
2. BUSY is asserted on port "B" blocking R/W
3. t
DATA
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
ADDR
ADDR
WH
WB
BUSY
L
R/W
OUT "B"
must be met for both BUSY input (SLAVE) and output (MASTER).
is only for the 'slave' version.
= CE
IN "A"
IL
"A"
"A"
"B"
"B"
for the reading port.
R
IL
= V
(slave), BUSY is an input. Then for this example BUSY
IL,
refer to Chip Enable Truth Table.
t
APS
(1)
BUSY
R/W
R/W
"A"
"B"
"B"
"B"
, until BUSY
APS
is ignored for M/S = V
"B"
goes HIGH.
t
WB
"A"
(3)
= V
t
BAA
IH
IL
and BUSY
(SLAVE).
MATCH
t
WC
11
t
WP
(2)
"B"
input is shown above.
t
WP
Industrial and Commercial Temperature Ranges
MATCH
IL
t
DW
t
WDD
)
t
WH
VALID
(1)
4850 drw 12
t
DDD
(3)
.
t
BDA
t
DH
IH
)
4850drw 11
t
BDD
(2,4,5)
VALID