IDT70V38L15PFI IDT [Integrated Device Technology], IDT70V38L15PFI Datasheet - Page 13

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IDT70V38L15PFI

Manufacturer Part Number
IDT70V38L15PFI
Description
HIGH-SPEED 3.3V 64K x 18 DUAL-PORT STATIC RAM
Manufacturer
IDT [Integrated Device Technology]
Datasheet
Waveform of Interrupt Timing
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. Refer to Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
5. Refer to Truth Table I - Chip Enable.
Truth Table IV — Interrupt Flag
NOTES:
1. Assumes BUSY
2. If BUSY
3. If BUSY
4. INT
5. Refer to Truth Table I - Chip Enable.
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
R/W
X
X
X
L
ADDR
ADDR
L
L
and INT
INT
R/W
CE
OE
L
R
CE
INT
= V
= V
"B"
"B"
"B"
"B"
"A"
CE
"A"
IL
R
IL
"A"
"B"
X
X
L
L
, then no change.
, then no change.
must be initialized at power-up.
L
L
= BUSY
Left Port
OE
R
X
X
X
L
=V
L
IH
.
A
15L
FFFF
FFFE
X
X
-A
0L
t
t
AS
AS
t
(3)
INTERRUPT CLEAR ADDRESS
(3)
t
INS
INR
INT
H
L
X
X
INTERRUPT SET ADDRESS
(3)
(2)
(3)
(3)
L
R/W
(1,5)
X
X
X
L
R
(1,4,5)
t
t
WC
RC
CE
13
X
X
L
L
R
Right Port
OE
X
X
X
L
R
(2)
(2)
t
WR
Industrial and Commercial Temperature Ranges
A
15R
FFFF
FFFE
(4)
X
X
-A
0R
INT
H
L
X
X
(2)
(3)
R
Set Right INT
Reset Right INT
Set Left INT
Reset Left INT
L
Function
R
Flag
L
Flag
R
Flag
4850 drw 15
4850 drw 16
Flag
4850 tbl 16

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