IDT70V38L15PFI IDT [Integrated Device Technology], IDT70V38L15PFI Datasheet - Page 6

• Manufacturer Part Number: IDT70V38L15PFI
• Description: HIGH-SPEED 3.3V 64K x 18 DUAL-PORT STATIC RAM
• Manufacturer: IDT [Integrated Device Technology]

AC Test Conditions
Timing of Power-Up Power-Down
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB or UB.
3. t
4. Start of valid data depends on which timing becomes effective last t
5. SEM = V
6. Refer to Truth Table I - Chip Enable.
DATA
BUSY
Waveform of Read Cycles
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
UB, LB
relation to valid output data.
ADDR
BDD
R/W
OUT
OUT
CE
OE
delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
(6)
IH
.
CE
I
I
CC
SB
(6)
t
t
t
t
t
AA
ACE
AOE
LZ
ABE
(1)
(4)
Figures 1 and 2
(4)
GND to 3.0V
(4)
(4)
(5)
3ns Max.
t
1.5V
1.5V
PU
AOE
, t
4850 tbl 11
ACE
t
RC
50%
, t
AA
t
or t
BDD
6
BDD
DATA
(3,4)
.
BUSY
Figure 1. AC Output Load
OUT
INT
435Ω
VALID DATA
Industrial and Commercial Temperature Ranges
t
PD
3.3V
4850 drw 03
(4)
590Ω
30pF
50%
DATA
t
HZ
(2)
t
OH
4850 drw 06
Figure 2. Output Test Load
OUT
* Including scope and jig.
(for t
435Ω
LZ
, t
.
HZ
, t
WZ
, t
3.3V
4850 drw 05
OW
4850 drw 04
)
590Ω
5pF*