BR25H010-W ROHM [Rohm], BR25H010-W Datasheet - Page 11

• Manufacturer Part Number: BR25H010-W
• Manufacturer: ROHM [Rohm]

●Method to cancel each command
○READ
○RDSR
○WRITE、PAGE WRITE
○WRSR
○WREN/WRDI
・Method to cancel : cancel by CSB = “H”
・Method to cancel : cancel by CSB = “H”
a：Ope code, address input area.
b：Data input area (D7~D1 input area)
c：Data input area (D0 area)
d：tE/W area.
a：From ope code to 15 rise.
b：From 15 clock rise to 16 clock rise (write enable area).
c：After 16 clock rise.
a：From ope code to 7-th clock rise, cancel by CSB = “H”.
b：Cancellation is not available when CSB is started after 7-th clock.
Cancellation is available by CSB=”H”
Cancellation is available by CSB=”H”
When CSB is started, write starts.
After CSB rise, cancellation cannot be made by any means.
Cancellation is available by CSB = “H”. However, when
write starts (CSB is started) in the area c, cancellation
cannot be made by any means. And by inputting on
SCK clock, cancellation cannot be made. In page write
mode, there is write enable area at every 8 clocks.
Note 1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore
Note 2) If CSB is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable,
Cancel by CSB =”H”.
When CSB is started, write starts.
After CSB rise, cancellation cannot be made by any means.
Cancel by CSB=”H”. However, when write starts (CSB is started)
in the area b, cancellation cannot be made by any means.
And, by inputting on SCK clock, cancellation cannot be made.
Note 1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once
Note 2) If CSB is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable,
write it once again.
therefore, it is recommended to fall in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or higher.
again
therefore, it is recommended to fall in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or higher.
11/16
SCK
SI
Fig.46 READ cancel valid timing
Ope code
Ope code
8 bit
Cancel available in all areas of read mode
8bit
D7
Fig.47 RDSR cancel valid timing
Fig.48 WRITE cancel valid timing
Fig.50 WREN/WRDI cancel valid timing
D6
Ope code
a
8 bit
Ope code
D5
8 bit
Cancel available in all
8bit/16bit
areas of read mode
Address
8 bit/16bit
Address
Fig.49 WRSR cancel valid timing
D4
b
SCK
a
D3
Ope code
8 bit
D2
a
8 bit
8 bit
a
Data
7
Data
D1
8 bit
14
a
Data
Data
8bit
D1
b
8
b
D0
b
15
D0
b
9
b
c
c
16
c
17
tE/W
tE/W
d
c