BR25H010-W ROHM [Rohm], BR25H010-W Datasheet - Page 15

• Manufacturer Part Number: BR25H010-W
• Manufacturer: ROHM [Rohm]

●Notes on power ON/OFF
●Noise countermeasures
●Cautions on use
○ At power ON/OFF, set CSB “H” (=Vcc).
○ Vcc noise (bypass capacitor)
○ SCK noise
○ WPB noise
(1)Described numeric values and data are design representative values, and the values are not guaranteed.
(3)Absolute maximum ratings
(4)GND electric potential
(5)Heat design
(6)Terminal to terminal short circuit and wrong packaging
(7)Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
○ LVCC circuit
○P.O.R. circuit
(2)We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by
changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and
fluctuations of external parts and our LSI.
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a
When the rise time (tR) of SCK is long, and a certain degree or more of noise exists, malfunction may occur owing to clock bit displacement.
If the absolute maximum ratings such as impressed voltage and operating temperature range and so forth are exceeded, LSI may be destructed. Do not impress
voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety
countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI.
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal.
In consideration of permissible dissipation in actual use condition, carry out heat design with sufficient margin.
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of short circuit
LVCC (Vcc-Lockout) circuit prevents data rewrite action at low power, and prevents wrong write.
At LVCC voltage (Typ. =1.9V) or below, it prevent data rewrite.
When CSB is “L”, this IC gets in input accept status (active). If power is turned on in this status, noises and the likes may cause malfunction,
mistake write or so. To prevent these, at power ON, set CSB “H”. (When CSB is in “H” status, all inputs are canceled.)
(Good example) CSB terminal is pulled up to Vcc.
(Bad example)
This IC has a POR (Power On Reset) circuit as mistake write countermeasure. After POR action, it gets in write disable status. The POR
circuit is valid only when power is ON, and does not work when power is OFF. When power is ON, if the recommended conditions of the
following tR, tOFF, and Vbot are not satisfied, it may become write enable status owing to noises and the likes.
And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
To avoid this, a Schmitt trigger circuit is built in SCK input. The hysterisis width of this circuit is set about 0.2V, if noises exist at SCK input,
set the noise amplitude 0.2Vp-p or below. And it is recommended to set the rise time (tR) of SCK 100ns or below. In the case when the rise
time is 100ns or higher, take sufficient noise countermeasures. Make the clock rise, fall time as small as possible.
During execution of write status register command, if there exist noises on WPB pin, mistake in recognition may occur and forcible
cancellation may result, which please note. To avoid this, a Schmitt trigger circuit is built in WPB input. In the same manner, a Schmitt trigger
circuit is built in SI input and HOLDB input too.
between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed.
bypass capacitor (0.1μF) between IC Vcc and GND. At that moment, attach it as close to IC as possible.
CSB terminal is “L” at power ON/OFF.
At power OFF, take 10ms or higher before supply. If power is turned on without observing this condition, the IC internal
circuit may not be reset, which please note.
In this case, CSB always becomes “L” (active status), and EEPROM may have malfunction, mistake write owing to
noises and the likes.
Even when CSB input is High-Z, the status becomes like this case, which please note.
Vcc
0
Vcc
CSB
GND
Fig.61 CSB timing at power ON/OFF
GND
Vcc
Vcc
Fig.62 Rise waveform
Good Example
tOFF
tR
Bad example
15/16
Vbot
Recommended conditions of t
10ms or below
100ms or below
t
R
10ms or higher
10ms or higher
R
, t
OFF
t
OFF
, Vbot
0.3V or below
0.2V or below
Vbot