IDT72V2101 IDT [Integrated Device Technology], IDT72V2101 Datasheet - Page 19

• Manufacturer Part Number: IDT72V2101
• Description: 3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO
• Manufacturer: IDT [Integrated Device Technology]

NOTES:
1. t
2. t
3. LD = HIGH, OE = LOW
4. n = PAE offset, m = PAF offset and D = maximum FIFO depth.
5. D = 262,145 for the IDT72V2101 and 524,289 for the IDT72V2111.
6. First word latency: t
D
Q
WCLK
RCLK
0
0
WEN
REN
PAE
t
t
- Q
PAF
- D
SKEW1
SKEW1
SKEW2
SKEW2
OR
HF
IR
8
8
, then OR assertion may be delayed one extra RCLK cycle.
, then the PAE deassertion may be delayed one extra RCLK cycle.
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH after one RCLK cycle plus t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that OR will go LOW after two RCLK cycles plus t
t
DS
t
ENS
W
1
DATA IN OUTPUT REGISTER
SKEW1
t
DH
t
+ 2*T
SKEW1
1
W
2
RCLK
(1)
+ t
2
REF
W
3
.
3
W
t
t
4
A
REF
t
DS
W
[n +2]
W
1
Figure 9. Write Timing (First Word Fall Through Mode)
t
W
SKEW2
1
[n+3]
t
PAE
(2)
W
2
[n+4]
W
[
]
t
DS
W
[
]
t
HF
W
[
]
W
[D-m-2]
REF
PAE
t
DS
. If the time between the rising edge of WCLK and the rising edge of RCLK is less than
. If the time between the rising edge of WCLK and the rising edge of RCLK is less than
W
[D-m-1]
W
[D-m]
1
W
[D-m+1]
t
PAF
W
[D-m+2]
W
[D-1]
W
D
t
WFF
4669 drw 12
t
ENH