IDT72V2101 IDT [Integrated Device Technology], IDT72V2101 Datasheet - Page 21

• Manufacturer Part Number: IDT72V2101
• Description: 3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO
• Manufacturer: IDT [Integrated Device Technology]

NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure. D = 262,144
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
Q
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
WCLK
for the IDT72V2101 and 524,288 for the IDT72V2111.
0
RCLK
WEN
1
REN
PAE
- Q
PAF
= first word written to the FIFO after Master Reset, W
HF
EF
RT
n
t
ENS
W
TM
x
262,144 x 9, 524,288 x 9
t
t
A
ENH
t
ENS
t
RTS
t
RTS
Figure 11. Retransmit Timing (IDT Standard Mode)
2
= second word written to the FIFO after Master Reset.
t
t
t
ENH
REF
HF
t
SKEW2
1
W
x+1
21
2
t
PAF
1
t
REF
t
ENS
2
t
t
A
PAE
COMMERCIAL AND INDUSTRIAL
W
TEMPERATURE RANGES
1
(3)
4669 drw 14
t
t
ENH
A
W
2
(3)