IDT72V2101 IDT [Integrated Device Technology], IDT72V2101 Datasheet - Page 9

• Manufacturer Part Number: IDT72V2101
• Description: 3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO
• Manufacturer: IDT [Integrated Device Technology]

IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
8
8
8
8
8
8
7
7
7
7
IDT72V2101 (262,144 x 9 BIT)
EMPTY OFFSET (MID-BYTE) REGISTER
FULL OFFSET (MID-BYTE) REGISTER
TM
EMPTY OFFSET (LSB) REGISTER
03H if LD is HIGH at Master Reset
00H if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
FFH if LD is HIGH at Master Reset
FULL OFFSET (LSB) REGISTER
7FH if LD is LOW at Master Reset
262,144 x 9, 524,288 x 9
7FH if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
00H if LD is LOW at Master Reset
DEFAULT VALUE
DEFAULT VALUE
DEFAULT VALUE
DEFAULT VALUE
2 1
2 1
Figure 3. Offset Register Location and Default Values
(MSB) REGISTER
(MSB) REGISTER
EMPTY OFFSET
FULL OFFSET
DEFAULT
DEFAULT
0H
0H
0
0
0
0
0
0
9
8
8
8
8
8
8
7
7
7
7
IDT72V2111 (524,288 x 9 BIT)
EMPTY OFFSET (MID-BYTE) REGISTER
FULL OFFSET (MID-BYTE) REGISTER
EMPTY OFFSET (LSB) REGISTER
FULL OFFSET (LSB) REGISTER
FFH if LD is HIGH at Master Reset
7FH if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
FFH if LD is HIGH at Master Reset
00H if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
7FH if LD is LOW at Master Reset
00H if LD is LOW at Master Reset
DEFAULT VALUE
DEFAULT VALUE
DEFAULT VALUE
DEFAULT VALUE
COMMERCIAL AND INDUSTRIAL
3
3
2
2
TEMPERATURE RANGES
(MSB) REGISTER
(MSB) REGISTER
EMPTY OFFSET
FULL OFFSET
DEFAULT
DEFAULT
0H
0H
4669 drw 06
0
0
0
0
0
0