SST25WF512-40-5I-SAE SST [Silicon Storage Technology, Inc], SST25WF512-40-5I-SAE Datasheet - Page 17

• Manufacturer Part Number: SST25WF512-40-5I-SAE
• Description: 512 Kbit / 1 Mbit / 2 Mbit / 4Mbit 1.8V SPI Serial Flash
• Manufacturer: SST [Silicon Storage Technology, Inc]

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
64-KByte Block-Erase for SST25WF020 and SST25WF040
The Block-Erase instruction clears all bits in the selected 64
KByte block to FFH. A Block-Erase instruction applied to a
protected memory area is ignored. Prior to any Write oper-
ation, the Write-Enable (WREN) instruction must be exe-
cuted. CE# must remain active low for the duration of any
command sequence. The Block-Erase instruction is initi-
ated by executing an 8-bit command, D8H, followed by
Chip-Erase
The Chip-Erase instruction clears all bits in the device to
FFH. A Chip-Erase instruction is ignored if any of the mem-
ory area is protected. Prior to any Write operation, the
Write-Enable (WREN) instruction must be executed. CE#
must remain active low for the duration of the Chip-Erase
instruction sequence. The Chip-Erase instruction is initiated
©2009 Silicon Storage Technology, Inc.
FIGURE 15: 64-KByte Block-Erase Sequence
FIGURE 16: Chip-Erase Sequence
SCK
CE#
SO
SI
MODE 3
MODE 0
SCK
CE#
SO
SI
MSB
0 1 2 3 4 5 6 7 8
MODE 3
MODE 0
D8
HIGH IMPEDANCE
HIGH IMPEDANCE
MSB
0 1 2 3 4 5 6 7
17
60 or C7
MSB
address bits [A
Significant Address) are used to determine block address
(BA
be driven high before the instruction is executed. Poll the
Busy bit in the software status register or wait T
completion of the internal self-timed Block-Erase. See Fig-
ure 15 for the Block-Erase sequences.
by executing an 8-bit command, 60H or C7H. CE# must be
driven high before the instruction is executed. The user may
poll the Busy bit in the software status register or wait T
for the completion of the internal self-timed Chip-Erase
cycle. See Figure 16 for the Chip-Erase sequence.
ADDR
X
), remaining address bits can be V
15 16
1328 F16.0
ADDR
23 24
23
-A
ADDR
0
]. Address bits [A
1328 F15.0
31
MS
IL
S71328-08-000
-A
or V
16
] (A
IH.
Data Sheet
MS
CE# must
BE
= Most
for the
11/09
CE