IDT79RC32332 IDT [Integrated Device Technology], IDT79RC32332 Datasheet - Page 5

• Manufacturer Part Number: IDT79RC32332
• Description: IDT Interprise Integrated Communications Processor
• Manufacturer: IDT [Integrated Device Technology]

Pin Description Table
a logic zero (low) level. All other signals (including clocks, buses and select lines) will be interpreted as being active, or asserted when at a logic one
(high) level.
System
CLKP
COLDRSTN
RSTN
SYSCLKP
Memory and Peripheral Bus
MADDR[25:0]
MDATA[31:0]
BDIRN
BOEN[1:0]
BRN
BGN
WAITACKN
CSN[5:0]
IDT 79RC32355
The following table lists the functions of the pins provided on the RC32355. Some of the functions listed may be multiplexed onto the same pin.
To define the active polarity of a signal, a suffix will be used. Signals ending with an “N” should be interpreted as being active, or asserted, when at
Name
Note: The input pads of the RC32355 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels.
This is especially critical for unused control signal inputs (such as BRN) which, if left floating, could adversely affect the RC32355’s opera-
tion. Also, any input pin left floating can cause a slight increase in power consumption.
Type I/O Type
I/O
I/O
O
O
O
O
O
O
I
I
I
I
[25:22] Low
[21:0] High
High Drive System clock output. This is a buffered and delayed version of the system clock input (CLKP). All SDRAM transactions
High Drive Memory Data Bus. 32-bit data bus for memory and peripheral accesses.
High Drive External Buffer Direction. External transceiver direction control for the memory and peripheral data bus, MDATA[31:0]. It
High Drive External Buffer Output Enable. These signals provide two output enable controls for external data bus transceivers on
High Drive
Low Drive
Drive with
Low Drive External Bus Grant. This signal is asserted low by RC32355 to indicate that RC32355 has relinquished ownership of the
Low Drive
with STI
Drive
Input
STI
[3:0]
[5:4]
STI
STI
STI
1
System Clock input. This is the system master clock input. The RISCore 32300 pipeline frequency is a multiple (x2, x3, or
x4) of this clock frequency. All other logic runs at this frequency or less.
Cold Reset. The assertion of this signal low initiates a cold reset. This causes the RC32355 state to be initialized, boot
configuration to be loaded, and the internal processor PLL to lock onto the system clock (CLKP).
Reset. This bidirectional signal is either driven low or tri-stated, an external pull-up is required to supply the high state. The
RC32355 drives RSTN low during a reset (to inform the external system that a reset is taking place) and then tri-states it.
The external system can drive RSTN low to initiate a warm reset, and then should tri-state it.
are synchronous to this clock. This pin should be externally connected to the SDRAMs and to the RC32355 SDCLKINP pin
(SDRAM clock input).
Memory Address Bus. 26-bit address bus for memory and peripheral accesses. MADDR[20:17] are used for the
SODIMM data mask enables if SODIMM mode is selected.
MADDR[22] Primary function: General Purpose I/O, GPIOP[27].
MADDR[23] Primary function: General Purpose I/O, GPIOP[28].
MADDR[24] Primary function: General Purpose I/O, GPIOP[29].
MADDR[25] Primary function: General Purpose I/O, GPIOP[30].
is asserted low during any read transaction, and remains high during write transactions.
the memory and peripheral data bus, MDATA. BOEN[0] is asserted low during external device read transactions. BOEN[1]
is asserted low during SDRAM read transactions.
External Bus Request. This signal is asserted low by an external master device to request ownership of the memory and
peripheral bus.
local memory and peripheral bus to an external master.
Wait or Transfer Acknowledge. When configured as wait, this signal is asserted low during a memory and peripheral
device bus transaction to extend the bus cycle. When configured as transfer acknowledge, this signal is asserted low dur-
ing a memory and peripheral device bus transaction to signal the completion of the transaction.
Device Chip Select. These signals are used to select an external device on the memory and peripheral bus during device
transactions. Each bit is asserted low during an access to the selected external device.
CSN[4] Primary function: General purpose I/O, GPIOP[16].
CSN[5] Primary function: General purpose I/O, GPIOP[17].
Table 1 Pin Descriptions (Part 1 of 8)
5 of 47
Description
May 25, 2004