HD3-15531B-9 INTERSIL [Intersil Corporation], HD3-15531B-9 Datasheet - Page 6

• Manufacturer Part Number: HD3-15531B-9
• Description: CMOS Manchester Encoder-Decoder
• Manufacturer: INTERSIL [Intersil Corporation]

ting the decoded data through SERIAL DATA OUT. The
decoded data available at SERIAL DATA OUT is in NRZ
format. The DECODER SHIFT CLOCK is provided so that
the decoded bits can get shifted into an external register on
every low-to-high transition of this clock
DECODER SHIFT CLOCK may adjust its phase up until the
time that TAKE DATA goes high.
After all K decoded bits have been transmitted
checked for parity. A high input on DECODER PARITY
SELECT will set the Decoder to check for even parity or a
low input will set the Decoder to check for odd parity. A high
SYNCHRONOUS
VALID WORD
DATA SYNC
TAKE DATA
COMMAND
DECODER
DATA OUT
BIPOLAR
BIPOLAR
ZERO IN
SERIAL
CLOCK
CLOCK
TIMING
ONE IN
SHIFT
SYNC
(MAY BE HIGH FROM PREVIOUS RECEPTION)
1ST HALF
0
SYNC
UNDEFINED
1
2ND HALF
SYNC
2
MSB
MSB
3
2
-
BIT K-1
BIT K-1
1
4
3
3
. Note that
the data is
BIT K-2
BIT K-2
FIGURE 2. DECODER
2
5
MSB
HD-15531
BIT K-3
BIT K-3
BITK-1
6
6
BIT K-4 BIT K-5
on VALID WORD output
of a word without any Manchester or parity errors. At this
time the Decoder is looking for a new sync character to start
another output sequence. VALID WORD will go low approx-
imately K + 4 DECODER SHIFT CLOCK periods after it
goes high, if not reset low sooner by a valid sync and two
valid Manchester bits as shown
At any time in the above sequence a high input on
DECODER RESET during a low-to-high transition of
DECODER SHIFT CLOCK will abort transmission and ini-
tialize the Decoder to start looking for a new sync character.
BIT K-4
BITK-2 BITK-3
7
BIT K-5
8
BIT 3
BIT 3
N-3
BIT 5
BIT 2
BIT 2
N-2
BIT 4
4
indicates a successful reception
BIT 1
BIT 1 PARITY
N-1
BIT 3
1
PARITY
.
N
BIT 2
BIT 1
3
4