m37280eksp Mitsumi Electronics, Corp., m37280eksp Datasheet - Page 21

• Manufacturer Part Number: m37280eksp
• Description: Single-chip 8-bit Cmos Microcomputer With Closed Caption Decoder And On-screen Display Controller
• Manufacturer: Mitsumi Electronics, Corp.

12.3 INTERRUPTS
Interrupts can be caused by 19 different sources consisting of 3 ex-
ternal, 14 internal, 1 software, and reset. Interrupts are vectored in-
terrupts with priorities as shown in Table 12.3.1. Reset is also in-
cluded in the table because its operation is similar to an interrupt.
When an interrupt is accepted,
Other interrupts are disabled when the interrupt disable flag is set to
“1.”
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits are
in interrupt request registers 1 and 2 and the interrupt enable bits are
in interrupt control registers 1 and 2. Figures 12.3.2 to 12.3.6 show
the interrupt-related registers.
Interrupts other than the BRK instruction interrupt and reset are ac-
cepted when the interrupt enable bit is “1,” interrupt request bit is “1,”
and the interrupt disable flag is “0.” The interrupt request bit can be
set to “0” by a program, but not set to “1.” The interrupt enable bit can
be set to “0” and “1” by a program.
Reset is treated as a non-maskable interrupt with the highest priority.
Figure 12.3.1 shows interrupt control.
Note : Switching a source during a program causes an unnecessary interrupt occurs. Accordingly, set a source at initializing of program.
Rev. 1.0
Table 12.3.1 Interrupt Vector Addresses and Priority
Priority
The contents of the program counter and processor status regis
ter are automatically stored into the stack.
The interrupt disable flag I is set to “1” and the corresponding
interrupt request bit is set to “0.”
The jump destination address stored in the vector address enters
the program counter.
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Reset
OSD interrupt
INT1 interrupt
Data slicer interrupt
Serial I/O interrupt
Timer 4 • SPRITE OSD interrupt
f(X
V
Timer 3 interrupt
Timer 2 interrupt
Timer 1 interrupt
A-D convertion • INT3 interrupt
INT2 interrupt
Multi-master I
Timer 5 • 6 interrupt
BRK instruction interrupt
SYNC
IN
)/4096 interrupt
interrupt
2
Interrupt Source
C-BUS interface interrupt
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
M37280MF–XXXSP, M37280MK–XXXSP
Vector Addresses
FFFD
FFEF
FFED
FFEB
FFDF
FFFF
FFFB
FFE9
FFE7
FFE5
FFE3
FFF9
FFF7
FFF5
FFF3
FFF1
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
, FFFE
, FFFC
, FFF8
, FFF6
, FFF4
, FFF2
, FFF0
, FFEE
, FFEC
, FFEA
, FFE8
, FFE6
, FFE4
, FFE2
, FFDE
, FFFA
12.3.1 Interrupt Causes
(1) V
(2) INT1, INT2 Interrupts
(3) Timer 1 to 4 Interrupts
The V
the vertical sync signal.
The OSD interrupt occurs after character block display to the
CRT is completed.
The INT1 and INT2 interrupts are external interrupt inputs, the
system detects that the level of a pin changes from LOW to HIGH
or from HIGH to LOW, and generates an interrupt request. The
input active edge can be selected by bits 3 and 4 of the interrupt
input polarity register (address 0212
change from LOW to HIGH is detected; when it is “1,” a change
from HIGH to LOW is detected. Note that both bits are cleared to
“0” at reset.
An interrupt is generated by an overflow of timer 1, 2, 3 or 4.
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
SYNC
SYNC
and OSD Interrupts
Non-maskable
Active edge selectable
Software switch by software (See note)
Active edge selectable
Software switch by software (See note)/
When selecting INT3 interrupt, active edge selectable.
Active edge selectable
Software switch by software (See note)
Non-maskable (software interrupt)
interrupt is an interrupt request synchronized with
and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
Remarks
M37280EKSP
16
) : when this bit is “0,” a
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