m37280eksp Mitsumi Electronics, Corp., m37280eksp Datasheet - Page 58

• Manufacturer Part Number: m37280eksp
• Description: Single-chip 8-bit Cmos Microcomputer With Closed Caption Decoder And On-screen Display Controller
• Manufacturer: Mitsumi Electronics, Corp.

12.10.2 Clamping Circuit and Low-pass Filter
The clamp circuit clamps the sync chip part of the composite video
signal input from the CV
of clamped composite video signal. The CV
video signal is input requires a capacitor (0.1 F) coupling outside.
Pull down the CV
M . In addition, we recommend to install externally a simple low-
pass filter using a resistor and a capacitor at the CV
Figure 12.10.1).
12.10.3 Sync Slice Circuit
This circuit takes out a composite sync signal from the output signal
of the low-pass filter.
12.10.4 Synchronous Signal Separation Circuit
This circuit separates a horizontal synchronous signal and a vertical
synchronous signal from the composite sync signal taken out in the
sync slice circuit.
(1)Horizontal Synchronous Signal (H
(2)Vertical Synchronous Signal (V
Figure 12.10.6 shows a V
shown in the figure is generated from the reference clock which the
timing generating circuit outputs.
Reading bit 5 of data slicer control register 2 permits determinating
the shape of the V-pulse portion of the composite sync signal. As
shown in Figure 12.10.7, when the A level matches the B level, this
bit is “0.” In the case of a mismatch, the bit is “1.”
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A one-shot horizontal synchronizing signal Hsep is generated at
the falling edge of the composite sync signal.
As a V
the following 2 methods by using bit 4 of the data slicer control
register 2 (address 00E1
•Method 1 The “L” level width of the composite sync signal is
•Method 2 The “L” level width of the composite sync signal is
sep
signal generating method, it is possible to select one of
measured. If this width exceeds a certain time, a V
signal is generated in synchronization with the rising
of the timing signal immediately after this “L” level.
measured. If this width exceeds a certain time, it is
detected whether a falling of the composite sync sig-
nal exits or not in the “L” level period of the timing
signal immediately after this “L” level. If a falling ex-
ists, a V
with the rising of the timing signal (refer to Fig-
ure12.10.6).
IN
pin with a resistor of hundreds of kiloohms to 1
IN
sep
pin. The low-pass filter attenuates the noise
sep
16
signal is generated in synchronization
).
generating timing. The timing signal
sep
sep
)
)
IN
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
pin to which composite
IN
pin (refer to
M37280MF–XXXSP, M37280MK–XXXSP
sep
Fig. 12.10.6 Vsep Generating Timing (method 2)
Composite s
Timing
signal
V
sep
A V
immediately after the “L” level width of the composite
sync signal exceeds a certain time.
signal
sep
signal is generated at a rising of the timing signal
and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
Measure “L” period
M37280EKSP
Rev. 1.0