em78p5842 ELAN Microelectronics Corp, em78p5842 Datasheet - Page 17
![no-image](/images/manufacturer_photos/0/2/215/elan_microelectronics_corp_sml.jpg)
em78p5842
Manufacturer Part Number
em78p5842
Description
8-bit Micro-controller
Manufacturer
ELAN Microelectronics Corp
Datasheet
1.EM78P5842.pdf
(45 pages)
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
R10~R3F (General Purpose Register)
Bit 3(INT0): By setting PORT70 to general IO, INT0 will define to PORT70 pin’s interrupt flag. If PORT70 has
Bit 4(INT1): By setting PORT71 to general IO, INT1 will define to PORT71 pin’s interrupt flag. External pull
PAGE 2,3 (undefined) not allowed to use.
RE (Interrupt flag)
PAGE0 (Interrupt flag)
PAGE2,3 (undefined) not allowed to use.
RF (Interrupt status)
(Interrupt status register)
"1" means interrupt request, "0" means non-interrupt
Bit 0(TCIF): TCC timer overflow interrupt flag
Bit 1(CNT1): counter1 timer overflow interrupt flag
Bit 2,5,6: Unused (These bits are not sure to 0 or 1. When programmer determine what interrupt occur in
Bit 7(INT3): External PORT73 pin interrupt flag. If PORT73 has a falling edge trigger signal, CPU will set this
R10~R3F (Banks 0 ~ 3) : all are general purpose registers.
R/W-0
R/W-0
PWM2
INT3
Bit0 ~ Bit3, Bit6: These four bits must clear to 0 or unable to expect error will occur .
Bit 4(PWM1) : PWM1 one period reach interrupt flag.
Bit 5 (ADI) : ADC interrupt flag after a sampling
Bit 7 (PWM2) : PWM2 (Pulse Width Modulation channel 2) interrupt flag
<Note> IOCF is the interrupt mask register. User can read and clear.
Trigger edge as the table
Set when a selected period is reached, reset by software.
Set when TCC timer overflows.
Set when counter1 timer overflows.
Signal
TCC
COUNTER1
INT0
INT1
INT3
7
7
a falling edge/rising edge (controlled by CONT register) trigger signal, CPU will set this bit. If setting
the pin to PLLC or OSCI, PORT70 interrupt will un-exist and INT0 register will be ignored.
high circuit is needed for PORT71 interrupt operation. If PORT71 has a falling edge trigger signal, CPU
will set this bit. If setting the pin to /RESET, PORT71 interrupt will un-exist and INT1 register will be
ignored.
R/W-X
R/W-0
subroutine, be care to note these bits)
bit.
0
0
6
6
Trigger
Time out
Time out
Falling
Rising edge
Falling edge
Falling edge
R/W-X
R/W-0
ADI
5
5
0
R/W-0
PWM1
R/W-0
INT1
4
4
R/W-0
R/W-0
INT0
0
3
3
15
R/W-X
R/W-0
0
0
2
2
R/W-0
CNT1
R/W-0
0
1
1
R/W-0
R/W-0
TCIF
0
0
0
EM785840/5841/5842
8-bit Micro-controller
2004/11/10 V1.2