k9f2g08q0m Samsung Semiconductor, Inc., k9f2g08q0m Datasheet - Page 10

• Manufacturer Part Number: k9f2g08q0m
• Description: 256m X 8 Bit / 128m X 16 Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

K9F2G08Q0M K9F2G16Q0M
K9F2G08U0M K9F2G16U0M
AC TEST CONDITION
(K9F2GXXX0M-XCB0 :TA=0 to 70 C, K9F2GXXX0M-XIB0:TA=-40 to 85 C
CAPACITANCE
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
NOTE : 1. X can be V
Program / Erase Characteristics
NOTE : 1. Max. time of
VALID BLOCK
NOTE :
1. The
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase
K9F2GXXQ0M : Vcc=1.70V~1.95V , K9F2GXXU0M : Vcc=2.7V~3.6V unless otherwise noted)
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
Input/Output Capacitance
Input Capacitance
Program Time
Dummy Busy Time for Cache Program
Number of Partial Program Cycles
in the Same Page
Block Erase Time
Valid Block Number
sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits
gram factory-marked bad blocks.
cycles.
CLE
H
H
X
X
X
X
X
L
L
L
L
device
2. WP and PRE should be biased to CMOS high or CMOS low for standby.
Parameter
may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-
Item
ALE
X
H
H
X
X
X
X
L
L
L
L
IL
(1)
t
or V
CBSY
Parameter
(
T
Parameter
IH.
A
=25 C, V
depends on timing between internal program completion and data in
CE
H
L
L
L
L
L
L
X
X
X
X
Refer to the attached technical notes for appropriate management of invalid blocks.
CC
=1.8V/3.3V, f=1.0MHz)
Symbol
Symbol
C
N
C
WE
H
X
X
X
X
X
I/O
VB
IN
Spare Array
Main Array
RE
Test Condition
H
H
H
H
H
H
X
X
X
X
V
V
2,008
1 TTL GATE and CL=30pF
IN
IL
Min
Symbol
=0V
=0V
t
t
t
PROG
CBSY
Nop
BERS
10
0V/V
K9F2GXXQ0M
WP
X
X
H
H
H
X
X
H
H
L
0V to Vcc
CC
Vcc/2
(2)
5ns
0V/V
Min
PRE
-
-
-
-
Typ.
Min
X
X
X
X
X
X
X
X
X
X
-
-
-
CC
(2)
Read Mode
Write Mode
Data Input
Data Output
During Read(Busy)
During Program(Busy)
During Erase(Busy)
Write Protect
Stand-by
Typ
300
3
2
-
-
FLASH MEMORY
1 TTL GATE and CL=50pF
2,048
Max
Max
10
10
Command Input
Address Input(5clock)
Command Input
Address Input(5clock)
K9F2GXXU0M
Mode
Max
0V to Vcc
700
700
4
4
3
Preliminary
. Do not erase or pro-
Vcc/2
5ns
Blocks
Unit
Unit
pF
pF
cycles
cycles
Unit
ms
s
s