k9f2g08q0m Samsung Semiconductor, Inc., k9f2g08q0m Datasheet - Page 34

• Manufacturer Part Number: k9f2g08q0m
• Description: 256m X 8 Bit / 128m X 16 Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

K9F2G08Q0M K9F2G16Q0M
K9F2G08U0M K9F2G16U0M
BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup
command(60h). Only address A
Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup
followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.
Figure 13. Block Erase Operation
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, the read command(00h) should be given before starting read cycles.
Table2. Read Staus Register Definition
NOTE :
R/B
I/Ox
I/O 8~15
(X16 device
I/O No.
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
only)
1. True Ready/Busy represents internal program operation status which is being executed in cache program mode.
2. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
Page Program
60h
Write Protect
Ready/Busy
Ready/Busy
Pass/Fail
Not Use
Not Use
Not use
Not use
Not use
Block Add. : A
Address Input(3Cycle)
18
to A
or A
Write Protect
Block Erase
Ready/Busy
Ready/Busy
28
Pass/Fail
11
12
Not Use
Not Use
Not use
Not use
Not use
(X8) or A
~ A
~ A
27
28
(X16)
(X8)
17
to A
D0h
True Ready/Busy
Cache Prorgam
27
Pass/Fail(N-1)
Write Protect
Pass/Fail(N)
(X16) is valid while A
Ready/Busy
Not Use
Not Use
Not use
Not use
34
t
BERS
Write Protect
12
Ready/Busy
Ready/Busy
Not Use
Not Use
Not use
Not use
Not use
Not use
to A
Read
17
(X8) or A
70h
11
Pass : "0"
Pass : "0"
Don’t -cared
Don’t -cared
Don’t -cared
Busy : "0"
Busy : "0"
Protected : "0"
Don’t -care
FLASH MEMORY
to A
16
(X16) is ignored. The Erase
Definition
Preliminary
I/O
Fail
0
Not Protected
"1"
Ready : "1"
Ready : "1"
Fail : "1"
Fail : "1"
"0"
Pass