ade3700 STMicroelectronics, ade3700 Datasheet - Page 46
ade3700
Manufacturer Part Number
ade3700
Description
Analog Lcd Display Engine For Xga And Sxga Resolutions
Manufacturer
STMicroelectronics
Datasheet
1.ADE3700.pdf
(89 pages)
Available stocks
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Part Number
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Quantity
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Part Number:
ade3700X
Manufacturer:
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Quantity:
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Output Sequencer
46/89
OSQ_CONTROL
OSQ_CLOCK_FRAC
OSQ_OUT_HTOTAL_L
OSQ_OUT_HTOTAL_H
OSQ_OUT_VTOTAL_MIN_L
OSQ_OUT_VTOTAL_MIN_H
OSQ_VTOTAL_MAX_L
OSQ_VTOTAL_MAX_H
OSQ_VERTEN_DLY_E_L
OSQ_VERTEN_DLY_E_M
OSQ_VERTEN_DLY_E_H
Register Name
alternate output sync pins (AHS, AUS, ADE) for applications that do not require the more
sophisticated timing control provided by the programmable TCON module.
Table 16: Output Sequencer Registers (Sheet 1 of 2)
0x0BC1
0x0BC2
0x0BC3
0x0BC4
0x0BC5
0x0BC6
0x0BC7
0x0BC8
0x0BC9
0x0BCA
0x0BCB
Addr
R
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mode
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[7:0]
[7:4]
[3:0]
[7:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:0]
[7:0]
[7:4]
[3:0]
Bits
[7:0]
[7:0]
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Default
OUT_VMAX detected, sticky bit
OUT_VMAX detect reset
Interlace Enable
Fractional Line Extend
0: +1
1: +2
Frame Lock Reference
0: Last Input Pixel
1: First Input Pixel
Frame Lock Selection
0: Last Line Variable
1: Fixed Line Length
Shutdown ready - current frame has completed,
panel can now be shut down
Run sequencer when 1, otherwise stop at the
end of the frame and set shutdown ready flag
(bit [1])
The fraction of lines (/256) that are extended
Nominal Output Horizontal Total [7:0]
Reserved
Nominal Output Horizontal Total [11:8]
minimum output vertical total, used to rearm for
vert_enab trigger [7:0]
Reserved
Minimum Output Vertical Total, used to rearm
for vert_enab triggers [11:8]
Maximum Output Vertical Total, prevents panel
burn with loss of vert_enab trigger [7:0]
Reserved
Maximum Output Vertical Total, prevents panel
burn with loss of vert_enab triggers [11:8]
Delay of the VERT_ENAB signal to the reset of
the horizontal and vertical counters, even and
non-interlaced modes [15:0]
Reserved
Delay of the VERT_ENAB signal to the reset of
the horizontal and vertical counters, even and
non-interlaced [19:16]
Description
ADE3700