ade3700 STMicroelectronics, ade3700 Datasheet - Page 74

• Manufacturer Part Number: ade3700
• Description: Analog Lcd Display Engine For Xga And Sxga Resolutions
• Manufacturer: STMicroelectronics

Output Multiplexer
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Enable Data OUT_MUX_CTRL0[0]
Enable
TCON
AB or BA
Double
Right Shift
Byte Flip
PWM enable OUT_MUX_CTRL3[1]
PWM mux
mode
OUT_MUX_CTRL1[3]
OUT_MUX_CTRL0[2]
OUT_MUX_CTRL0[1]
OUT_MUX_CTRL1[2:0]
OUT_MUX_CTRL0[4]
OUT_MUX_CTRL3[2]
OBA7
OBA6
OBA5
OBA4
OBA3
OBA2
OBA1
OBA0
OGA7
OGA6
OGA5
OGA4
OGA3
OGA2
OGA1
OGA0
ORA7
ORA6
ORA5
ORA4
ORA3
ORA2
ORA1
last point the data is flopped with DCLK before the pins
gated clock available from tcon_srtd[12] in tcon mode
see tables 2.2 - 2.5 for configurations.
Table 27: Output Mux Specification (Sheet 1 of 2)
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BDA7 BDA7 PWMA BDA7 BDA7 BDA7 BDA7 BDA7
BDA6 BDA6 BDA6 BDA6 BDA6 BDA6 BDA6 BDA6
BDA5 BDA5 BDA5 BDA5 BDA5 BDA5 BDA5 BDA5
BDA4 BDA4 BDA4 BDA4 BDA4 BDA4 BDA4 BDA4
BDA3 BDA3 BDA3 BDA3 BDA3 BDA3 BDA3 BDA3
BDA2 BDA2 BDA2 BDA2 BDA2 BDA2 BDA2 BDA2
BDA1 BDA1 BDA1 BDA1 BDA1 BDA1 BDA1 BDA1
BDA0 BDA0 BDA0 PWMA BDA0 BDA0 BDA0 BDA0
GDA7 GDA7 PWMB GDA7 GDA7 GDA7 GDA7 GDA7
GDA6 GDA6 GDA6 GDA6 GDA6 GDA6 GDA6 GDA6
GDA5 GDA5 GDA5 GDA5 GDA5 GDA5 GDA5 GDA5
GDA4 GDA4 GDA4 GDA4 GDA4 GDA4 GDA4 GDA4
GDA3 GDA3 GDA3 GDA3 GDA3 GDA3 GDA3 GDA3
GDA2 GDA2 GDA2 GDA2 GDA2 GDA2 GDA2 GDA2
GDA1 GDA1 GDA1 GDA1 GDA1 GDA1 GDA1 GDA1
GDA0 GDA0 GDA0 PWMB GDA0 GDA0 GDA0 GDA0
RDA7 RDA7 RDA7 RDA7 RDA7 RDA7 RDA7 TCI11
RDA6 RDA6 RDA6 RDA6 RDA6 RDA6 RDA6 RDA6
RDA5 RDA5 RDA5 RDA5 RDA5 RDA5 RDA5 RDA5
RDA4 RDA4 RDA4 RDA4 RDA4 RDA4 RDA4 RDA4
RDA3 RDA3 RDA3 RDA3 RDA3 TCI11 RDA3 RDA3
RDA2 RDA2 RDA2 RDA2 RDA2 TCI10 RDA2 RDA2
RDA1 PWMA RDA1 RDA1 RDA1
X
X
X
1
0
0
1
1
X
X
X
1
1
0
1
1
>0
1
1
X
1
0
1
1
>0
X
1
1
1
1
1
1
X
X
X
1
1
0
0
0
TCI9
1
1
1
0
X
X
0
X
RDA1 RDA1
X
X
X
1
1
1
0
0
>0
1
1
X
0
X
1
0
ADE3700
BDA7
BDA6
BDA5
BDA4
BDA3
BDA2
BDA1
BDA0
GDA7
GDA6
GDA5
GDA4
GDA3
GDA2
GDA1
GDA0
RDA7
RDA6
RDA5
RDA4
RDA3
RDA2
RDA1
>0
X
X
1
1
1
1
0