sza1000 NXP Semiconductors, sza1000 Datasheet - Page 18

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sza1000

Manufacturer Part Number
sza1000
Description
Qic Digital Equalizer
Manufacturer
NXP Semiconductors
Datasheet

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C
Address 37: Main clock divider
Table 27 Clock divider: CLK_DIV; note 1
Note
1. CD selects the main clock division factor. The CLKIN frequency (pin 6) divided by this factor gives the IC’s operating
Table 28 Clock division factor
S
Address 38: Stripe detector nominal frequency
Table 29 Qualification threshold: STRIPE_F; note 1
Note
1. SF is an unsigned 5-bit value used to determine the detection threshold for the stripe detector. The nominal detection
AUXBUS,
Address 39: Equalizer mode settings
Table 30 EQ_MODE 1; note 1, see also Tables 31 to 34
Note
1. R1 selects the filter sample rate reduction factor; STBY1 and STBY2 are the DAC and ADC power on/off switches;
1998 Feb 16
TRIPE DETECTOR FUNCTIONS
LOCK FUNCTIONS
QIC digital equalizer
frequency f
frequency is
ST selects output signal modes for pins 25 and 27.
D7
D7
D7
PINS
CD
0
1
2
3
4
5
6
7
s
25
(apart from the WEQ circuit).
--------------------------------- -
3
AND
STBY2
D6
D6
D6
SF
f
27,
s
+
SAMPLE RATE REDUCTION AND STAND
1
CLOCK DIVISION
ST.3
D5
D5
D5
1
2
3
4
5
6
7
8
SF.4
ST.2
D4
D4
D4
18
-
BY FUNCTIONS
SF.3
ST.1
D3
D3
D3
CD.2
SF.2
ST.0
D2
D2
D2
STBY1
CD.1
SF.1
D1
D1
D1
Product specification
SZA1000
CD.0
SF.0
D0
D0
D0
R1

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