sza1000 NXP Semiconductors, sza1000 Datasheet - Page 7

• Manufacturer Part Number: sza1000
• Description: Qic Digital Equalizer
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Stripe detector
This circuit is used to signal the stripes in QIC 3080,
QIC 3095 and TR4 servo formats (STRIPE output on
pin 21 must be selected; see Table 22). A frequency
detector counts the peaks above the qualification
threshold (see Table 29). An input signal containing
frequencies within 25% of the programmable nominal
frequency will be detected as a stripe. The microcontroller
can then poll the amplitude of the following burst via the
serial interface.
Differentiator
This function is realized by subtracting samples. The delay
between samples is programmable between 1 and 6
periods of f
delay between the differentiated and non-differentiated
signals (see Tables 24 to 26).
The PLL
This is a fully digital PLL (Phase Lock Loop) with a
programmable nominal frequency (see Tables 35 and 36),
zero phase restart, programmable window shift
(WIN_SHIFT; control register address 42) and a loop filter
with two separate programmable settings.
The PLL output reference clock is the RRC signal (pin 25;
see Table 34). The frequency of this signal is rounded in
time to f
RG (pin 20) is LOW, and makes a zero phase restart at the
first detected peak after RG goes HIGH.
The LTD input (pin 19) is used to select between the two
loop filter settings (see Tables 37 to 42). This allows for
fast lock-in during preamble, before switching to a lower
loop bandwidth for maximum data reliability (see Fig.3).
1998 Feb 16
handbook, halfpage
QIC digital equalizer
INPUT
SIGNALS
RG
LTD
PLL
MODE
s
. The PLL is switched to the nominal frequency if
s
nominal
frequency
, split into two parts to provide a balanced
Fig.3 PLL timing diagram.
preamble
fast lock-in
zero phase restart
normal read mode
data
MGG583
7
The maximum likelihood detector
This detector calculates the most likely position of the
peaks in the signal. It checks for (d,k) code constraints,
and for alternating peaks. If an error is detected, the ‘most
likely’ correction is implemented.
Separate corrections can be enabled or disabled.
The SRD output of the maximum likelihood detector is
valid during the rising edge of the RRC signal (see Fig.4).
The maximum likelihood detector is used only to generate
the SRD signal, and not to generate the time continuous
RD pulse.
The DAC
This is an internal differential 8-bit DAC operating at f
The LPF after the DAC
This analog LPF filters the time quantized signal from the
DAC to retain a time continuous signal. This provides more
accurate timing of the detected zero crossings in the RD
pulse output.
The LPF is a second order active filter with a cut-off
frequency of 8 MHz.
The read pulse circuit
A peak in the equalized signal at the interpolator output
generates a read pulse. The peak is detected if a zero
crossing occurs in the filtered signal after the DAC while
the non-differentiated signal is above the qualification
threshold.
Uncommitted current sources
Two uncommitted 5-bit programmable current sink DACs
(0 to 2 mA) are available as IO1 and IO2 (see Table 20 for
programming). These could be used, for example, to drive
the tape hole detector circuit.
handbook, halfpage
SRD
RRC
Fig.4 SRD/RRC timing.
Product specification
SZA1000
MGG584
s
.