lxt384 Intel Corporation, lxt384 Datasheet - Page 38

• Manufacturer Part Number: lxt384
• Description: Octal T1/e1/j1 Short Haul Transceiver
• Manufacturer: Intel Corporation

Intel
38
Table 12. Configuration and Mode-Select Signals (Sheet 2 of 2)
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
MODE
MUX
TNEG7 /
TNEG6 /
TNEG5 /
TNEG4 /
TNEG3 /
TNEG2 /
TNEG1 /
TNEG0 /
1. DI: Digital Input
Signal
Name
UBS7
UBS6
UBS5
UBS4
UBS3
UBS2
UBS1
UBS0
QFP
144
102
109
Pin
43
72
79
31
38
11
7
PBGA
Ball
D12
N12
B12
L12
E2
K2
B3
D3
N3
L3
I/O
DI
DI
DI
1
Mode Select Input.
MODE is used to select the type of operating mode the LXT384
Transceiver uses, as shown in the following table.
Note: VCC/2 can be obtained by connecting to a resistive divider
For details on modes in the table, see the following:
Multiplexed/Non-Multiplexed Select Input.
When the LXT384 Transceiver is in parallel interface host
processor mode, and MUX is:
In hardware mode, tie this unused input low.
For timing diagrams, see
Parallel Interface
Unipolar/Bipolar Select Input 7:0.
For information on the UBS signals, see
Mapper
• In Hardware Mode (low), the parallel processor interface is
• In Parallel Host Mode (high), the parallel port interface pins
• In Serial Host mode (VCC/2), the serial interface pins: SDI,
•
•
•
• Low, operation is in non-multiplexed mode.
• High, operation is in multiplexed mode.
MODE
VCC/2
High
Low
disabled and hard-wired pins are used to control configuration
and report status.
are used to control configuration and report status.
SDO, SCLK, and CS are used.
Section 7.2, “Hardware Mode”
Section 7.4.1, “Host Processor Mode - Parallel Interface”
Section 7.4.2, “Host Processor Mode - Serial Interface”
consisting of two 10 kΩ resistors across V
Signals”.
Hardware mode
Host Processor mode - Parallel
interface
Host Processor mode - Serial interface
Timing”.
Operating Mode
Signal Description
Section 11.2, “Host Processor Mode -
Revision Date: September 22, 2005
Section 5.3, “Framer/
Document Number: 248994
Revision Number: 004
CC
and Ground.