cx82100 Conexant Systems, Inc., cx82100 Datasheet - Page 208

• Manufacturer Part Number: cx82100
• Description: Home Network Processor Hnp
• Manufacturer: Conexant Systems, Inc.

Figure 13-1. Clock Generation Block Diagram
13-2
on BCLKIO
on FCLKIO
PLL_BP
XFCLK
XBCLK
CLKI
CX82110 HNP
PLL_B Prescale Select
PLL_F Prescale Select
(PLL_B_PRE)
(PLL_F_PRE)
Pre-Scaler
Pre-Scaler
Divide by
3, 4, or 5
Divide by
3, 4, or 5
Conexant Proprietary and Confidential Information
Divide
Divide
Divide
Divide
Mode Clock Divider
by 2
by 4
by 2
by 4
(LPM_CLK_DIV)
Mode Clock
Low Power
Low Power
Divider
CX82100 Home Network Processor Data Sheet
(PLL FCLK/2)
(PLL BCLK/2)
PLL Bypass Mode
PLL Bypass Mode
Detector
Detector
Phase
Phase
(PLL_BP Pin
(PLL_BP Pin
PLL UCLK
PLL BCLK
PLL PCLK
PLL FCLK
XFCLK/2
XFCLK/4
XBCLK/2
XBCLK/4
Phase Detector
Phase Detector
Divide by M.N
Divide by M.N
Divide
Divide
by 2
by 4
0
1
0
1
0
1
0
1
and Loop Filter
and Loop Filter
Charge Pump
Charge Pump
Mode Enable
Low Power
(LPM_EN)
Mode Enable
Low Power
(LPM_EN)
0
1
0
1
BCLK Generation Logic (Post BCLK PLL)
FCLK Generation Logic (Post FCLK PLL)
VCO
VCO
UCLK
(PLL_F_CR_SLOW )
Speed Select
FCLK Slow
Divide
Divide
by 2
by 4
0
1
(PLL_B_CR_SLOW )
Speed Select
(Divide by 2)
(Divide by 4)
(Divide by 2)
(Divide by 4)
BCLK Slow
O utput
Divider
O utput
Divider
O utput
Divider
O utput
Divider
0
1
0
1
PLL FCLK
PLL FCLK/2
PLL BCLK
PLL BCLK/2
BCLK PLL
FCLK PLL
(by 3, 4, or 5
or 1 or 2)
EPCLK Clock
(PLL_B_CR)
EPCLK
Rate Select
Divider
Rate Indicate
(PLL_F_CR)
(12 MHz)
Interface
USB Clock
FCLK
PCLK
BCLK
USB
EPCLK
on BCLKIO
UCLK
on FCLKIO
HL_CLK
101545_064
101306C