or3l165b Lattice Semiconductor Corp., or3l165b Datasheet - Page 24

• Manufacturer Part Number: or3l165b
• Description: Orca Or3lxxxb Series Field-programmable Gate Arrays
• Manufacturer: Lattice Semiconductor Corp.

ORCA OR3LxxxB Series FPGAs
Timing Characteristics
Table 13. Microprocessor Interface (MP I) Timing Characteristics (continued)
OR3LxxB Commercial: V
to 3.6 V, V
10. User should set up read data so that RDS_SET and RDS_HLD can be met for the microprocessor timing.
Notes:
Read and write descriptions are referenced to the host microprocessor; e.g., a read is a read by the host (PowerPC, i960) from the FPGA.
PowerPC and i960 timings to/from the clock are relative to the clock at the FPGA microprocessor interface clock pin (MPI_CLK).
24
i960 Interface Timing (T
User Logic Delay
Synchronous User Timing
Asynchronous User Timing
1. For user system flexibility,
2. 0.5 MPI_CLK.
3. Write data and W/R have to be valid starting from the clock cycle after both ADS and CS0 and CS1 are recognized.
4. Write data and W/R have to be held until the microprocessor receives a valid RDYRCV.
5. User Logic Delay has no predefined value. The user must generate a UEND signal to complete the cycle.
6. USTART_DEL is based on the falling clock edge.
7. There is no specific time associated with this delay. The user must assert UEND low to complete this cycle.
8. The user must assert interrupt request low until a service routine is executed.
9. This should be at least one MPI_CLK cycle.
USTARTCLR_DEL User Start Clear Delay (MPI_CLK to USTART)
when
CS1 may go inactive before the end of the read/write cycle.
USTART_DEL
URDWR_DEL
UEND_HLD
UEND_DEL
UEND_SET
TUIRQ_PW
RDS_SET
RDS_HLD
RDA_DEL
RDA_HLD
RW_SET
RW_HLD
CS_SET
CS_HLD
UA_DEL
Symbol
MPI_STRB
DD
2 = 2.38 V to 2.63 V, –40 °C
is low. If both chip selects are valid and the setup time is met, the MPI will latch the chip select state, and
5
Read/Write Setup Time
Read/Write Hold Time
Chip Select Setup Time (CS0, CS1 to CLK)
Chip Select Hold Time (CS0, CS1 from CLK)
User Address Delay (CLK low to UA[3:0])
User Read/Write Delay (pad to URDWR_DEL)
User Start Delay (MPI_CLK falling to USTART)
User End Delay (USTART low to UEND low)
User End Setup (UEND to MPI_CLK)
User End Hold (UEND to MPI_CLK)
Data Setup for Read (D[7:0] to MPI_CLK)
Data Hold for Read (D[7:0] from MPI_CLK)
User End to Read Data Delay (UEND to D[7:0])
Data Hold from User Start (low)
Interrupt Request Pulse Width
CS0
DD
J
= 85 °C, V
and CS1 may be set up to any one of the three rising clock edges, beginning with the rising clock edge
= 3.0 V to 3.6 V, V
(continued)
DD
<
= min, V
T
A
4
Parameter
3
DD
<
+85 °C.
2 = 2.38 V to 2.63 V, 0 °C
DD
2 = min) (continued)
8
9
9
1
9
7
1
6
10
<
T
A
<
0.80
1.40
Min Max Min Max
0.0
0.0
—
—
—
—
—
—
—
—
—
—
—
—
70 °C; Industrial: V
–7
6.21
4.60
3.80
6.90
—
—
—
—
—
—
—
—
—
—
—
—
Lattice Semiconductor
0.70
1.20
0.0
0.0
Data Addendum
—
—
—
—
—
—
—
—
—
—
—
—
–8
5.40
4.00
3.30
6.00
March 2002
—
—
—
—
—
—
—
—
—
—
—
—
DD
CS0
= 3.0 V
and
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns