or3l165b Lattice Semiconductor Corp., or3l165b Datasheet - Page 36

• Manufacturer Part Number: or3l165b
• Description: Orca Or3lxxxb Series Field-programmable Gate Arrays
• Manufacturer: Lattice Semiconductor Corp.

ORCA OR3LxxxB Series FPGAs
Timing Characteristics
Table 22. Derating for Commercial/Industrial
OR3Lxxx Devices (I/O Supply V
Table 23. Derating for Commercial/Industrial
OR3Lxxx Devices (I/O Supply V
Note: The derating tables shown above are for a typical critical path
36
–40
100
125
–40
100
125
(°C)
(°C)
T
25
85
T
25
85
0
0
J
J
that contains 33% logic delay and 66% routing delay. Since the
routing delay derates at a higher rate than the logic delay, paths
with more than 66% routing delay will derate at a higher rate
than shown in the table. The approximate derating values vs.
temperature are 0.26% per °C for logic delay and 0.45% per °C
for routing delay. The approximate derating values vs. voltage
are 0.13% per mV for both logic and routing delays at 25 °C.
3.0 V
2.3 V
0.82
0.91
0.98
1.00
1.23
1.34
0.86
0.94
0.99
1.00
1.23
1.33
Power Supply Voltage
Power Supply Voltage
3.3 V
2.5 V
0.72
0.80
0.85
0.99
1.07
1.15
0.71
0.79
0.84
0.99
1.05
1.13
(continued)
DD
DD
)
2)
2.6 V
3.6 V
0.66
0.72
0.77
0.90
0.94
1.01
0.67
0.73
0.77
0.92
0.96
1.03
In addition to supply voltage, process variation, and
operating temperature, circuit and process improve-
ments of the ORCA Series FPGAs over time will result
in significant improvement of the actual performance
over those listed for a speed grade. Even though lower
speed grades may still be available, the distribution of
yield to timing parameters may be several speed
grades higher than that designated on a product brand.
Design practices need to consider best-case timing
parameters (e.g., delays = 0), as well as worst-case
timing.
The routing delays are a function of fan-out and the
capacitance associated with the CIPs and metal inter-
connect in the path. The number of logic elements that
can be driven (fan-out) by PFUs is unlimited, although
the delay to reach a valid logic level can exceed timing
requirements. It is difficult to make accurate routing
delay estimates prior to design compilation based on
fan-out. This is because the CAE software may delete
redundant logic inserted by the designer to reduce fan-
out, and/or it may also automatically reduce fan-out by
net splitting.
Lattice Semiconductor
Data Addendum
March 2002