hd66100 Renesas Electronics Corporation., hd66100 Datasheet - Page 231

• Manufacturer Part Number: hd66100
• Description: H8/3867 Series
• Manufacturer: Renesas Electronics Corporation.

9.5.2
1. Timer counter (TCG)
TCG is an 8-bit up-counter which is incremented by clock input. The input clock is selected by
bits CKS1 and CKS0 in TMG.
TMIG in PMR1 is set to 1 to operate TCG as an input capture timer, or cleared to 0 to operate
TCG as an interval timer*. In input capture timer operation, the TCG value can be cleared by the
rising edge, falling edge, or both edges of the input capture input signal, according to the setting
made in TMG.
When TCG overflows from H'FF to H'00, if OVIE in TMG is 1, IRRTG is set to 1 in IRR2, and if
IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see 3.3, Interrupts.
TCG cannot be read or written by the CPU. It is initialized to H'00 upon reset.
Note: * An input capture signal may be generated when TMIG is modified.
2. Input capture register GF (ICRGF)
ICRGF is an 8-bit read-only register. When a falling edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGF. If IIEGS in TMG is 1 at this time,
IRRTG is set to 1 in IRR2, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2ø or 2ø
ICRGF is initialized to H'00 upon reset.
216
Bit:
Initial value:
Read/Write:
Bit:
Initial value:
Read/Write:
Register Descriptions
ICRGF7
TCG7
—
R
7
0
7
0
SUB
ICRGF6
TCG6
—
R
6
0
6
0
(when the noise canceler is not used).
ICRGF5
TCG5
—
R
5
0
5
0
ICRGF4
TCG4
—
R
4
0
4
0
ICRGF3
TCG3
—
R
3
0
3
0
ICRGF2
TCG2
—
R
2
0
2
0
ICRGF1
TCG1
—
R
1
0
1
0
ICRGF0
TCG0
—
R
0
0
0
0