hd66100 Renesas Electronics Corporation., hd66100 Datasheet - Page 57

• Manufacturer Part Number: hd66100
• Description: H8/3867 Series
• Manufacturer: Renesas Electronics Corporation.

2.6
CPU operation is synchronized by a system clock (ø) or a subclock (ø
clock signals see section 4, Clock Pulse Generators. The period from a rising edge of ø or ø
the next rising edge is called one state. A bus cycle consists of two states or three states. The
cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
2.6.1
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing
access in byte or word size. Figure 2.11 shows the on-chip memory access cycle.
42
ø or ø
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Internal data bus
(write access)
Basic Operational Timing
Access to On-Chip Memory (RAM, ROM)
SUB
Figure 2.11 On-Chip Memory Access Cycle
T
1
state
Bus cycle
Address
Write data
Read data
T
2
state
SUB
). For details on these
SUB
to