mx25l12805d Macronix International Co., mx25l12805d Datasheet - Page 14

• Manufacturer Part Number: mx25l12805d
• Description: 128m-bit [x 1] Cmos Serial Flash
• Manufacturer: Macronix International Co.

Table 4. Protection Modes
Note:
1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.
As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).
Software Protected Mode (SPM):
-
-
P/N: PM1310
(5) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write
Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR
instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as
shown in table 1). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in accordance with Write
Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is
entered.
The sequence of issuing WRSR instruction is: CS# goes low-> sending WRSR instruction code-> Status Register data
on SI-> CS# goes high. (see Figure 16)
The WRSR instruction has no effect on b6, b1, b0 of the status register.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-
timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress
(WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing,
and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
Software protection
mode(SPM)
Hardware protection
mode (HPM)
When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change the values
of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected
mode (SPM).
When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP3,
BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM)
Mode
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
bits can be changed
The SRWD, BP0-BP3 of
status register bits cannot be
changed
Status register condition
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
WP# and SRWD bit status
14
WP#=0, SRWD bit=1
MX25L12805D
The protected area cannot
be program or erase.
The protected area cannot
be program or erase.
Memory
REV. 1.1, OCT. 01, 2008