SI4133 ETC, SI4133 Datasheet - Page 18

• Manufacturer Part Number: SI4133
• Description: Dual-band RF Synthesizer WITH Integrated VCOS FOR Wireless Communications
• Manufacturer: ETC

S i4 13 3
Applications where the PLL is regularly powered-down
or the frequency is periodically reprogrammed minimize
or eliminate the potential effects of temperature drift
because the VCO is re-tuned in either case. In
applications where the ambient temperature can drift
substantially after self-tuning, it may be necessary to
monitor the lock-detect bar (LDETB) signal on the
AUXOUT pin to determine whether a PLL is about to
run out of locking capability. (See “Auxiliary Output
(AUXOUT)”
signal will be low after self-tuning has completed but will
rise when either the IF or RF PLL nears the limit of its
compensation range. (LDETB will also be high when
either PLL is executing the self-tuning algorithm.) The
output frequency will still be locked when LDETB goes
high, but the PLL will eventually lose lock if the
temperature continues to drift in the same direction.
Therefore, if LDETB goes high both the IF and RF PLLs
should promptly be re-tuned by initiating the self-tuning
algorithm.
Output Frequencies
The IF and RF output frequencies are set by
programming the R- and N-Divider registers. Each PLL
has its own R and N registers so that each can be
programmed independently. Programming either the R-
or N-Divider register for RF1 or RF2 automatically
selects the associated output.
The reference frequency on the XIN pin is divided by R
and this signal is input to the PLL’s phase detector. The
other input to the phase detector is the PLL’s VCO
output frequency divided by N. The PLL acts to make
these frequencies equal. That is, after an initial transient
or
The R values are set by programming the RF1 R-
Divider register (Register 6), the RF2 R-Divider register
(Register 7) and the IF R-Divider register (Register 8).
The N values are set by programming the RF1 N-
Divider register (Register 3), the RF2 N-Divider register
(Register 4), and the IF N-Divider register (Register 5).
Each N-Divider is implemented as a conventional high
speed divider. That is, it consists of a dual-modulus
prescaler, a swallow counter, and a lower speed
synchronous counter. However, the control of these
sub-circuits
appropriate N value should be programmed.
18
for how to select LDETB.) The LDETB
is
handled
f
OUT
f
----------- -
OUT
N
=
=
N
--- - f
R
automatically.
f
-----------
REF
R
REF
Only
the
Rev. 1.1
PLL Loop Dynamics
The transient response for each PLL is determined by
its phase detector update rate f (equal to f
the phase detector gain programmed for each RF1,
RF2, or IF synthesizer. (See Register 1.) Four different
settings for the phase detector gain are available for
each PLL. The highest gain is programmed by setting
the two phase detector gain bits to 00, and the lowest by
setting the bits to 11. The values of the available gains,
relative to the highest gain, are as follows:
The gain value bits can be automatically set by setting
the Auto K
to 1. In setting this bit, the gain values will be optimized
for a given value of N. In general, a higher phase
detector gain will decrease in-band phase noise and
increase the speed of the PLL transient until the point at
which stability begins to be compromised. The optimal
gain depends on N. Table 9 lists recommended settings
for different values of N. These are the settings used
when the Auto K
The VCO gain and loop filter characteristics are not
programmable.
The settling time for the PLL is directly proportional to its
phase detector update period T (T equals 1/f ). A
typical transient response is shown in Figure 6 on page
11. During the first 13 update periods the Si4133
executes the self-tuning algorithm. Thereafter the PLL
16384 to 32767
8192 to 16383
2048 to 4095
4096 to 8191
32768
2047
N
Table 8. Gain Values (Register 1)
P
Table 9. Optimal K
bit (bit 2) in the Main Configuration register
K
P
P
00
01
10
11
Bits
bit is set.
K
P1
RF1
00
00
00
01
10
11
<1:0>
Relative P.D.
K
P
P2
Gain
Settings
RF2
00
00
01
10
1/2
1/4
1/8
11
11
<3:2>
1
REF
K
PI
/R) and
<5:4>
00
01
10
11
11
11
IF