SI4133 ETC, SI4133 Datasheet - Page 19

• Manufacturer Part Number: SI4133
• Description: Dual-band RF Synthesizer WITH Integrated VCOS FOR Wireless Communications
• Manufacturer: ETC

controls the output frequency. Because of the unique
architecture of the Si4133 PLLs, the time required to
settle the output frequency to 0.1 ppm error is only
about 25 update periods. Thus, the total time after
power-up or a change in programmed frequency until
the synthesized frequency is well settled—including
time for self-tuning—is around 40 update periods.
Note: The settling time analysis holds for RF1 f
RF and IF Outputs
The RFOUT and IFOUT pins are driven by amplifiers
that buffer the RF VCOs and IF VCO, respectively. The
RF output amplifier receives its input from either the
RF1 or RF2 VCO, depending upon which R- or N-
Divider register was last written. For example,
programming
automatically selects the RF1 VCO output.
Figures 13 and 14 show application diagrams for the
Si4133. The RF output signal must be AC coupled to its
load through a capacitor. An external inductance
between the RFOUT pin and the AC coupling capacitor
is required as part of an output matching network to
maximize power delivered to the load. This 2 nH
inductance may be realized with a PC board trace. The
network is made to provide an adequate match to an
external 50
bands. The matching network also filters the output
signal to reduce harmonic distortion.
The IFOUT pin must also be AC coupled to its load
through a capacitor. The IF output level is dependent
upon the load. Figure 18 on page 20 displays the output
level versus load resistance for a variety of output
frequencies. For resistive loads greater than 500
output level saturates and the bias currents in the IF
output amplifier are higher than they need to be. The
LPWR bit in the Main Configuration register (Register 0)
can be set to 1 to reduce the bias currents and therefore
reduce the power dissipated by the IF amplifier. For
loads less than 500
maximize the output level.
For IF frequencies greater than 500 MHz, a matching
network is required in order to drive a 50
Figure 16 below. The value of L
determined from Table 10.
Frequency
500–600 MHz
600–800 MHz
800 MHz–1 GHz
For RF1 f > 500 kHz, the settling time is larger.
Table 10. L
load for both the RF1 and RF2 frequency
the
N-Divider
LPWR should be set to 0 to
MATCH
Values
register
L
40 nH
27 nH
18 nH
MATCH
MATCH
for
load. See
can be
500 kHz.
RF1
the
Rev. 1.1
For frequencies less than 500 MHz, the IF output buffer
can directly drive a 200
resistive loads greater than 500
LPWR bit can be set to reduce the power consumed by
the IF output buffer. See Figure 17 below.
Reference Frequency Amplifier
The Si4133 provides a reference frequency amplifier. If
the driving signal has CMOS levels it can be connected
directly to the XIN pin. Otherwise, the reference
frequency signal should be AC coupled to the XIN pin
through a 560 pF capacitor.
Power Down Modes
Table 11 summarizes the power down functionality. The
Si4133 can be powered down by taking the PWDNB pin
low or by setting bits in the Power Down register
(Register 2). When the PWDNB pin is low, the Si4133 will
be powered down regardless of the Power Down register
settings. When the PWDNB pin is high, power
management is under control of the Power Down register
bits.
The IF and RF sections of the Si4133 circuitry can be
individually powered down by setting the Power Down
register bits PDIB and PDRB low, respectively. Note that
the reference frequency amplifier will also be powered up if
either the PDRB and PDIB bits are high. Also, setting the
AUTOPDB bit to 1 in the Main Configuration register
(Register 0) is equivalent to setting both bits in the Power
Down register to 1.
The serial interface remains available and can be written in
all power down modes.
IFOUT
Figure 16. IF Frequencies > 500 MHz
Figure 17. IF Frequencies < 500 MHz
IFOUT
L
MATCH
>500 pF
resistive load or higher. For
560 pF
(f < 500 MHz) the
>200
Si4133
50
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