D485505G NEC [NEC], D485505G Datasheet - Page 14

• Manufacturer Part Number: D485505G
• Description: LINE BUFFER 5K-WORD BY 8-BIT
• Manufacturer: NEC [NEC]

4.2 n Bit Delay
(1) Perform a reset operation in the cycle proportionate to the delay length. (Figure 4.3)
(2) Shift the input timing of write reset (RSTW) and read reset (RSTR) depending on the delay length. (Figure 4.4)
(3) Shift the address by disabling RE for the period proportionate to the delay length. (Figure 4.5)
Restrictions
to 2. Operation Mode Operation-related Restriction.
14
WCK/RCK
(Output)
RSTW /
It is possible to make delay read from the write data with the PD485505.
n bit: Delay bits from write cycle to read cycle correspond to a same address cell.
Delay bits n can be set from minimum bits to maximum bits depending on the operating cycle time. Refer
Remark RE, WE = “L” level
(Input)
(Input)
(Input)
RSTR
Read
Write
D
D
OUT
IN
t
t
t
WCW
RCW
RS
Cycle 0
t
t
t
WCK
RCK
RH
t
t
t
WCP
RCP
DS
(0)
t
DH
Cycle time
Cycle 1
25 ns
35 ns
Figure 4.3 n-Bit Delay Line Timing Chart (1)
(n Cycles)
(1)
Cycle 2
1 H
Data Sheet M10059EJ7V0DS00
(2)
t
WAR
21 bits
15 bits
MIN.
(n–2)
Cycle n–1
(n–1)
t
RS
Cycle 0’
Cycle 0
t
RH
t
AC
5,048 bits
5,048 bits
MAX.
t
DS
(0’)
(0)
t
t
DH
Cycle 1’
OH
Cycle 1
(n Cycles)
(1’)
2 H
(1)
Cycle 2’
Cycle 2
(2’)
Cycle 3’
Cycle 3
(2)
PD485505
(3’)
(3)