m65761fp Renesas Electronics Corporation., m65761fp Datasheet - Page 10

• Manufacturer Part Number: m65761fp
• Description: Assp>ics For Audio Accessory>karaoke Processors Qm-coder
• Manufacturer: Renesas Electronics Corporation.

M65761FP
Description of Registers
(1) System set up register (W/R)
(Address: 0)
d0 (HR):
d1, d2 (MOD):
d3 (CX):
d4 (BS):
d5 (BX):
Table 1 The Coed Data and Image Data Lineup on the Host Bus
Note:
b6 (PI):
b7 (PB):
Table 2 The Image Data Lineup on the Image Data Parallel Bus
Note:
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
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Bus Width
Bit Width
BUS16
PB = 0
PB = 1
16-bit
8-bit
b0 is the first coded data on the time series/the left-hand side image data on the screen.
b15 is the last coded data on the time series/the right-hand image data on the screen.
p0 is the image data on the left-hand on the screen.
p31 is the image data on the right-hand on the screen.
1
0
SYS_REG:
This sets up the operating modes.
Select data bit swap of the host bus. (0: MSB (d7) first, 1: LSB (d0) first)
Select data byte swap of the host bus. (0: Lower byte (A) first, 1: Upper byte (B) first)
Selects the image data I/O I/F (0: Serial I/F, 1: Parallel I/F)
H/W reset (0: Active, 1: Reset state)
To make a H/W reset, set this bit to 1 then to 0.
Reset initializes the entire LSI including the group of register and line memory. However, the
context table RAM is not initialized.
d2 = 0, d1 = 1: decoding, d2 = 1, d1 = 1: lage data through (Host I/F lage data I/F))
Context select (0: internal context, 1: Image data through)
Note: The internal context should be selected when the image data through mode is used.
Note: BX is valid only when the host bus is 16 bits. (BUS16 = HIGH)
Selects the bit width of the image data bus (0: 32-bit bus (PD0 to 31), 1: 16-bit bus (PD0 to 15))
(d2 = 0, d1 = 0: coding, d2 = 1, d1 = 0: lage data through (lage data I/F Host I/F),
d7 (MSB)
BX
—
—
0
0
1
1
PD31
PB
p0
When initializing or processing R/W of the context table RAM and coding/decoding.
This bit must be set the same. (Because RAM configuration changes depending on
internal/external modes.)
Swap
BS
0
1
0
1
0
1
PI
• • • • •
• • • • •
—
d15
b15
b8
b0
b7
BX
Upper Address (B)
PD16
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
p15
—
—
BS
b15
d8
b8
b7
b0
CX
PD15
p16
p0
b15
d7
b0
b7
b8
b0
b7
• • • • •
• • • • •
• • • • •
Lower Address (A)
MOD
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
PD0
p31
p15
b15
HR
d0
b7
b0
b8
b7
b0
d0