at1212 Arrive Technologies, Inc., at1212 Datasheet
at1212
Manufacturer Part Number
at1212
Description
Oc-12 Multi-service Adm
Manufacturer
Arrive Technologies, Inc.
Datasheet
1.AT1212.pdf
(2 pages)
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US
© 2007 Arrive Technologies All Rights Reserved
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SONET/SDH. The chip supports a dual OC-12/STM-4 SONET/SDH interface with 1+1 or UPSR/SNCP hardware controlled protection. On
A
D
supports an OIF SPI-3 bus to support external devices such as a Network Processor to provide extended L2+ or L3 level processing or
84 DS1/J1
63 E1
3 DS3/E3
N
UPSR, 1+1
N
SONET/SDH mapping, SONET/SDH/PDH virtual concatenation (VCAT) and LCAS with 128 groups in accordance with G.7041, G.8040,
the Ethernet side, the chip provides 8 Fast Ethernets via a SMII/SS-SMII bus and 2 Gigabit Ethernet ports with on-chip CDRs. It also
common legacy data over PDH, PDH mapped to SONET/SDH or direct SONET mapping. On the PDH side, the chip provides a parallel
4xOC‐3/
STM‐4/
OC‐12/
STM‐1
9xEC‐1
connects supporting DS0, VT/TU/TU3 and STS/VC level switching. The AT1212 provides a multi-format and multi-rate Ethernet and
expansion of the Ethernet ports. The AT1212 supports ATM, GFP-T/F, HDLC, PPP and LAPS encapsulation. A Traffic Aggregation and
3xEC‐1
Dual
P
u
Management at Layer 2 for VLAN/MPLS with Classifying, Policing, Queuing, Shaping, and Scheduling is provided. It provides direct
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u
T
T
multiplexed PDH bus carrying 3 DS3s or 3 E3s or 84 DS1s or 63 E1s or any mixture of them. The 84/63 DS1/E1s signals can be
The AT1212 is a highly integrated OC-12/STM-4 Multiservice Add/Drop Multiplexer on a chip. The AT1212 has integrated cross-
accessed directly via the PDH bus or be multiplexed to 3 channelized DS3/E3s via 3 embedded M13/E13 engines or mapped to
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integrated ADM/MSPP
PDH/SONET/SDH
private line backhaul systems
Next Generation MSPP, MSTP or ADM systems
Next Generation ultra low cost micro and pizza box MSPPs/ADMs
SONET/SDH Enterprise Customer Premises Equipment with
Line-cards for SONET/SDH Switches and Cross-connects
Multi-rate/multi-format Mapping of Ethernet over PDH or
Ideal for cost sensitive wireless backhaul and Ethernet/PDH
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w
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x
x
OC‐12 (W)
C
SONET/SDH
SONET/SDH
C
EC‐1
OC‐12 (E)
LIUs
PDH
LIUs
D
D
SFP
SFP
G.7042 and G.7043. A serial port is provided for ESCON, DVB-ASI or low speed Fiber Channel SAN applications.
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OC-12 Multi-Service ADM
Rev. 1.3 – May 2008
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Interface
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r
FPGA
PDH
SONET/SDH Drop
T
o
T
SONET/SDH NW
o
w
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A
A
A
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N
Direct EC‐1
N
O
T
T
O
Interface
Interface
Interface
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T
1
-
-
1
1
1
1
1
M
M
2
2
2
2
S
S
2
2
N
N
1
1
1
1
2
2
PDH
2
2
Bus
.
S
S
1
1
2
P
2
P
AGG DDR2
SDRAMs
Ext DS0
SONET/SDH
PDH
SPI
Ethernet
Serial Data
Ext DS0
SONET/SDH
PDH
SPI
Ethernet
Serial Data
P
P
a
Duplex A
Duplex B
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A
r
VCAT DDR2
T
T
SDRAMs
1
1
2
r
2
1
1
Ethernet A/B
Serial Data A/B
Ext DS0 A/B
SONET/SDH A/B
PDH A/B
SPI A/B
2
2
i
ZBT SSRAM
DS0/ VT/TU
v
Processor
Network
w/ CDR
GE/FE
or LIU
LIUs
(NP)
PHY
PHY
SFP
GbE CDR
Interface
SS‐SMII
SMII/
SPI‐3
SAN
e
Ext DS0 I/F
Ext VT/TU I/F
OC‐3/EC‐1
DS3/DS1
E3/E1
GE/FE
GE/FE
ESCON/DVB‐ASI
Low Speed FC
Ethernet PHY
Expansion
Ethernet
t
SAN
PHY
GbE
SFP
NP/
e
Ethernet
8x10/100
10/100/1000
2 ESCON
Ethernet
DVB‐ASI
2x1Gb
c
LS FC
Ethernet
h
n
K
K
S
S
OC‐12 (W)
OC‐12 (E)
i
i
E
E
m
m
o
Y
Y
p
on a chip
TU11/TU12/TU2, and 8K-DS0 cross-connects
FC/FICON/ESCON and DVB-ASI ports
with LCAS
and 12 EC-1s
VLAN/MPLS with Classifying, Policing, Queuing, Shaping
and Scheduling
connected at SPI-3 port
(can be eliminated if VCAT is not utilized)
(can be eliminated if Data Aggregation is not utilized)
p
622 Mbps SONET/SDH Data & PDH Multi-Service ADM
2xOC-12/STM-4 SONET/SDH network interfaces
4xOC-3/STM-1 SONET/SDH drop interfaces
622Mbps SONET/SDH drop muxed interface for 9xEC-1
3xEC-1 serial drop interfaces
Supports Hardware based APS for Linear and UPSR/SNC
Includes STS/VC, TU3, VT1.5/VT2/VT3/VT6/
Integrated Fast Ethernet and Gigabit Ethernet,
Supports 128 SONET/SDH HI/LO and PDH VCAT Groups
Transparent and Frame GFP mapping
OIF SPI-3 port with up to 128 logical channels
Integrated 3xDS3/E3 and 84/63xDS1/E1 framers
Integrated Network side framers for 2xOC-12/STM-1s
Integrated Drop side framers for 4xOC-3/STM-1s,
Traffic Aggregation and Management at Layer 2 for
E-LAN/VPLS is supported via an external FPGA or ASIC
Integrated system synchronization
2x16Mx16 DDR2 SDRAM for VCAT delay compensation
3x32Mx16 DDR2 SDRAM for Data Aggregation buffer
1x512Kx36 ZBT SSRAM for hardware status
Provided in an HFC-BGA1296 package
Typical power consumption is 5-7 watts
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E
x
x
o
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T
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1
1
2
2
g
U
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i
1
1
c
c
2
2
R
R
r
r
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o
o
E
E
-
-
S
S
M
M
e
Ext DS0
Serial Data
SONET/SDH
PDH
SPI
Ethernet
S
S
s
P
P
Preliminary Short Data Sheet
P
P
.
c
o
Ext DS0 I/F
FPGA
VT/TU I/F
Eth MAC
m
w/CDR
or LIU
GE/FE
PHY
PHY
SFP
NP
VIETNAM
LIUs
Ext DS0 I/F
Ext VT/TU I/F
OC‐3/EC‐1
GE/FE
GE/FE
ESCON/DVB‐ASI
Low Speed FC
Page 1
DS3/DS1
E3/E1
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at1212 Summary of contents
Page 1
... OIF SPI-3 bus to support external devices such as a Network Processor to provide extended L2 level processing or expansion of the Ethernet ports. The AT1212 supports ATM, GFP-T/F, HDLC, PPP and LAPS encapsulation. A Traffic Aggregation and Management at Layer 2 for VLAN/MPLS with Classifying, Policing, Queuing, Shaping, and Scheduling is provided. It provides direct SONET/SDH mapping, SONET/SDH/PDH virtual concatenation (VCAT) and LCAS with 128 groups in accordance with G ...
Page 2
OC-12 Multi-Service ADM Rev. 1.3 – May 2008 ...