74LVC86APW,118 NXP Semiconductors, 74LVC86APW,118 Datasheet

IC QUAD 2IN EXC-OR GATE 14TSSOP

74LVC86APW,118

Manufacturer Part Number
74LVC86APW,118
Description
IC QUAD 2IN EXC-OR GATE 14TSSOP
Manufacturer
NXP Semiconductors
Series
74LVCr
Datasheets
1.74LVC86ADB118.pdf (15 pages)
2.74LVC86APW118.pdf (15 pages)

Specifications of 74LVC86APW,118

Number Of Circuits
4
Package / Case
14-TSSOP
Logic Type
XOR (Exclusive OR)
Number Of Inputs
2
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Product
OR
Logic Family
LVC
High Level Output Current
- 24 mA
Low Level Output Current
24 mA
Propagation Delay Time
3 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.2 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Logical Function
XOR
Number Of Elements
4
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Operating Temp Range
-40C to 125C
Package Type
TSSOP
Number Of Outputs
1
Technology
CMOS
Mounting
Surface Mount
Pin Count
14
Operating Temperature Classification
Automotive
Quiescent Current
40uA
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
1.2V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74LVC86APW-T
74LVC86APW-T
935250110118
1. General description
2. Features
3. Ordering information
Table 1:
Type number
74LVC86AD
74LVC86ADB
74LVC86APW −40 °C to +125 °C TSSOP14
74LVC86ABQ
Ordering information
Package
Temperature
range
−40 °C to +125 °C SO14
−40 °C to +125 °C SSOP14
−40 °C to +125 °C DHVQFN14
The 74LVC86A provides four 2-input EXCLUSIVE-OR functions. It is a high-performance,
low power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
74LVC86A
Quad 2-input EXCLUSIVE-OR gate
Rev. 05.00 — 15 May 2006
5 V tolerant inputs for interlacing with 5 V logic
Supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard JESD8-B / JESD36
ESD protection:
Specified from −40 °C to +85 °C and −40 °C to 125 °C
HBM JESD22-A114-C exceeds 2000 V
CDM JESD22-C101-C exceeds 1000 V
Name
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced very thin
quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
Product data sheet
Version
SOT108-1
SOT337-1
SOT402-1
SOT762-1

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74LVC86APW,118 Summary of contents

Page 1

Quad 2-input EXCLUSIVE-OR gate Rev. 05.00 — 15 May 2006 1. General description The 74LVC86A provides four 2-input EXCLUSIVE-OR functions high-performance, low power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. ...

Page 2

Philips Semiconductors 4. Functional diagram mna787 Fig 1. Logic diagram Fig 3. Logic diagram for one gate 5. Pinning information ...

Page 3

Philips Semiconductors 5.2 Pin description Table 2: Pin description Symbol Pin GND ...

Page 4

Philips Semiconductors 7. Limiting values Table 4: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V ...

Page 5

Philips Semiconductors 9. Static characteristics Table 6: Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter = −40 °C to +85 °C T amb V HIGH-level input voltage LOW-level ...

Page 6

Philips Semiconductors …continued Table 6: Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter V HIGH-level output OH voltage V LOW-level output voltage input leakage current I I supply ...

Page 7

Philips Semiconductors Table 7: Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter = 25 °C T amb C power dissipation capacitance PD per gate. [1] Typical values are measured at T ...

Page 8

Philips Semiconductors negative positive Test data is given in Table 8. Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance ...

Page 9

Philips Semiconductors 12. Package outline SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT ...

Page 10

Philips Semiconductors SSOP14: plastic shrink small outline package; 14 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1.80 ...

Page 11

Philips Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 ...

Page 12

Philips Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area ...

Page 13

Philips Semiconductors 13. Abbreviations Table 9. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model TTL Transistor Transistor Logic 14. Revision history Table 10. Revision history ...

Page 14

Philips Semiconductors 15. Legal information 15.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

Page 15

Philips Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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