sh66k51a SinoWealth Micro-Electronics Corp. Ltd, sh66k51a Datasheet - Page 8

• Manufacturer Part Number: sh66k51a
• Description: 2k 4-bit Micro-controller With Lcd Driver
• Manufacturer: SinoWealth Micro-Electronics Corp. Ltd

Functional Descriptions
1. CPU
The CPU contains the following functional blocks:
Program Counter (PC), Arithmetic Logic Unit (ALU), Carry
Flag (CY), Accumulator, Table Branch Register, Data
Pointer (INX, DPH, DPM, and DPL) and Stacks.
1.1. PC
The PC is used for ROM addressing consisting of 12-bit:
Page Register (PC11), and Ripple Carry Counter (PC10,
PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0).
The program counter is loaded with data corresponding
to each instruction. The unconditional jump instruction
(JMP) can be set at 1-bit page register for higher than 2K.
The program counter cans only 4K program ROM
address. (Refer to the ROM description).
1.2. ALU and CY
The ALU performs arithmetic and logic operations. The
ALU provides the following functions:
Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, SBI)
Decimal adjustments for addition/subtraction (DAA, DAS)
Logic operations (AND, EOR, OR, ANDIM, EORIM, ORIM)
Decisions (BA0, BA1, BA2, BA3, BAZ, BNZ, BC, BNC)
Logic Shift (SHR)
The Carry Flag (CY) holds the ALU overflow that the
arithmetic operation generates. During an interrupt
service or CALL instruction, the carry flag is pushed into
the stack and recovered from the stack by the RTNI
instruction. It is unaffected by the RTNW instruction.
1.3. Accumulator (AC)
The accumulator is a 4-bit register holding the results of
the arithmetic logic unit. In conjunction with the ALU, data
is transferred between the accumulator and system
register, or data memory can be performed.
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1.4. Table Branch Register (TBR)
Table Data can be stored in program memory and can be
referenced by using Table Branch (TJMP) and Return
Constant (RTNW) instructions. The TBR and AC are
placed by an offset address in program ROM. TJMP
instruction branch into address ((PC11 - PC8) X (28) +
(TBR, AC)). The address is determined by RTNW to
return look-up value into (TBR, AC). ROM code bit7-bit4
is placed into TBR and bit3-bit0 into AC.
1.5. Data Pointer
The Data Pointer can indirectly address data memory.
Pointer address is located in register DPH (3-bit), DPM
(3-bit) and DPL (4-bit). The addressing range can have
3FFH locations. Pseudo index address (INX) is used to
read or write Data memory, then RAM address bit9 - bit0
which comes from DPH, DPM and DPL.
1.6. Stack
The stack is a group of registers used to save the
contents of CY & PC (11-0) sequentially with each
subroutine call or interrupt. The MSB is saved for CY and
it is organized into 13 bits X 4 levels. The stack is
operated on a first-in, last-out basis and returned
sequentially to the PC with the return instructions
(RTNI/RTNW).
Note:
The stack nesting includes both subroutine calls and
interrupts requests. The maximum allowed for subroutine
calls and interrupts are 4 levels. If the number of calls and
interrupt requests exceeds 4, then the bottom of stack will
be shifted out, that program execution may enter an
abnormal state.
SH66K51A